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| author | Miodrag Milanović <mmicko@gmail.com> | 2020-07-16 18:07:58 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-16 18:07:58 +0200 |
| commit | 910f4213247a69e1214aac70a552eec0a21d4275 (patch) | |
| tree | e36ea01f3eaaeda369c9b2f32f6d01e4c1d3fefb /tests/arch | |
| parent | b74eb598bc7dbf76d3308155a709325b820c4e99 (diff) | |
| parent | 3050454d6e80ddb7603f7d5cc117b440a6bd8ab8 (diff) | |
| download | yosys-910f4213247a69e1214aac70a552eec0a21d4275.tar.gz yosys-910f4213247a69e1214aac70a552eec0a21d4275.tar.bz2 yosys-910f4213247a69e1214aac70a552eec0a21d4275.zip | |
Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogic
anlogic: Use dfflegalize.
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/anlogic/latches.ys | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/tests/arch/anlogic/latches.ys b/tests/arch/anlogic/latches.ys index 8d66f77b3..34a3b14d0 100644 --- a/tests/arch/anlogic/latches.ys +++ b/tests/arch/anlogic/latches.ys @@ -3,31 +3,33 @@ design -save read hierarchy -top latchp proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_anlogic +equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic +design -load postopt cd latchp # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT3 -select -assert-none t:AL_MAP_LUT3 %% t:* %D +select -assert-count 1 t:AL_MAP_SEQ +select -assert-count 1 t:AL_MAP_LUT1 +select -assert-none t:AL_MAP_SEQ t:AL_MAP_LUT1 %% t:* %D design -load read hierarchy -top latchn proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_anlogic +equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic +design -load postopt cd latchn # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT3 -select -assert-none t:AL_MAP_LUT3 %% t:* %D +select -assert-count 1 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_SEQ %% t:* %D design -load read hierarchy -top latchsr proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_anlogic +equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic +design -load postopt cd latchsr # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT5 -select -assert-none t:AL_MAP_LUT5 %% t:* %D +select -assert-count 1 t:AL_MAP_SEQ +select -assert-count 2 t:AL_MAP_LUT3 +select -assert-none t:AL_MAP_SEQ t:AL_MAP_LUT3 %% t:* %D |