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* tests: Centralize test collection and Makefile generationXiretza2020-09-217-133/+21
* intel_alm: Add multiply signedness to cellsDan Ravensloft2020-08-262-6/+44
* techmap/shift_shiftx: Remove the "shiftx2mux" special path.Marcelina Kościelnicka2020-08-201-2/+3
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-077-31/+28
* opt_expr: Remove -clkinv option, make it the default.Marcelina Kościelnicka2020-07-311-2/+1
* synth_ice40: Use opt_dff.Marcelina Kościelnicka2020-07-301-1/+1
* synth_xilinx: Use opt_dff.Marcelina Kościelnicka2020-07-301-9/+7
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-271-0/+6
* intel_alm: increase abc9 -WDan Ravensloft2020-07-261-6/+6
* satgen: Add support for dffe, sdff, sdffe, sdffce cells.Marcelina Kościelnicka2020-07-241-2/+0
* intel_alm: add additional ABC9 timingsDan Ravensloft2020-07-231-6/+4
* Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogicMiodrag Milanović2020-07-161-12/+14
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| * anlogic: Use dfflegalize.Marcelina Kościelnicka2020-07-141-12/+14
* | Revert "intel_alm: direct M10K instantiation"Lofty2020-07-131-6/+0
* | xilinx: Fix srl regression.Marcelina Kościelnicka2020-07-121-0/+41
* | gowin: Use dfflegalize.Marcelina Kościelnicka2020-07-062-13/+8
* | intel_alm: direct M10K instantiationDan Ravensloft2020-07-051-0/+6
* | synth_gowin: ABC9 supportDan Ravensloft2020-07-051-1/+5
* | intel_alm: add Cyclone 10 GX testsDan Ravensloft2020-07-0511-2/+236
* | intel_alm: DSP inferenceDan Ravensloft2020-07-051-0/+23
* | synth_intel_alm: Use dfflegalize.Marcelina Kościelnicka2020-07-041-1/+1
* | Improve MISTRAL_FF specify rulesDan Ravensloft2020-07-041-1/+2
* | tests: update fsm.ys resource countEddie Hung2020-07-041-4/+4
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* intel_alm: fix DFFE matchingDan Ravensloft2020-06-112-4/+4
* Add missing .gitignore fileClaire Wolf2020-06-041-0/+2
* Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-4/+53
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| * abc9_ops: update messaging (credit to @Xiretza for spotting)Eddie Hung2020-05-301-4/+4
| * tests: add test for abc9 -dff removing a redundant flop entirelyEddie Hung2020-05-251-0/+15
| * tests: add testcase for abc9 -dff preserving flop namesEddie Hung2020-05-251-0/+34
* | Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixesEddie Hung2020-06-031-0/+13
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| * | tests: tidy up testcaseEddie Hung2020-06-031-3/+0
| * | tests: add ecp5 latch testcase with -abc9Eddie Hung2020-05-251-0/+16
* | | Merge pull request #2080 from YosysHQ/eddie/fix_test_warningsEddie Hung2020-06-032-2/+2
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| * | | tests: fix some test warningsEddie Hung2020-05-252-2/+2
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* | | allow range for mux testMiodrag Milanovic2020-06-011-1/+2
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* | tests: xilinx macc test to have initval, shorten BMC depth for runtimeEddie Hung2020-05-252-8/+8
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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-191-2/+4
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-5/+29
* abc9: suppress warnings when no compatible + used flop boxes formedEddie Hung2020-05-141-1/+3
* xilinx: update abc9_dff testsEddie Hung2020-05-141-18/+45
* xilinx: remove no-longer-relevant testEddie Hung2020-05-141-91/+0
* intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-071-0/+20
* intel_alm: work around a Quartus ICEDan Ravensloft2020-04-231-0/+12
* tests: read +/xilinx/cell_sim.v before xilinx_dsp testEddie Hung2020-04-221-0/+1
* test: ice40_dsp test to read +/ice40/cells_sim.v for default paramsEddie Hung2020-04-221-0/+1
* xilinx: xilinx_dffopt to read cells_sim.v; fix testEddie Hung2020-04-221-13/+22
* tests: remove write_ilangEddie Hung2020-04-202-3/+0
* synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-1510-0/+208
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-105-35/+551
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| * ecp5: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-16/+62
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