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* intel_alm: Add multiply signedness to cellsDan Ravensloft2020-08-262-6/+44
| | | | | | Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
* techmap/shift_shiftx: Remove the "shiftx2mux" special path.Marcelina Kościelnicka2020-08-201-2/+3
| | | | | | | | | | | | | | Our techmap rules for $shift and $shiftx cells contained a special path that aimed to decompose the shift LSB-first instead of MSB-first in select cases that come up in pmux lowering. This path was needlessly overcomplicated and contained bugs. Instead of doing that, just switch over the main path to iterate LSB-first (except for the specially-handled MSB for signed shifts and overflow handling). This also makes the code consistent with shl/shr/sshl/sshr cells, which are already decomposed LSB-first. Fixes #2346.
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-077-31/+28
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* opt_expr: Remove -clkinv option, make it the default.Marcelina Kościelnicka2020-07-311-2/+1
| | | | | Adds -noclkinv option just in case the old behavior was actually useful to someone.
* synth_ice40: Use opt_dff.Marcelina Kościelnicka2020-07-301-1/+1
| | | | | | | | | The main part is converting ice40_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the mux patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* synth_xilinx: Use opt_dff.Marcelina Kościelnicka2020-07-301-9/+7
| | | | | | | | | The main part is converting xilinx_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-271-0/+6
| | | | This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
* intel_alm: increase abc9 -WDan Ravensloft2020-07-261-6/+6
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* satgen: Add support for dffe, sdff, sdffe, sdffce cells.Marcelina Kościelnicka2020-07-241-2/+0
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* intel_alm: add additional ABC9 timingsDan Ravensloft2020-07-231-6/+4
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* Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogicMiodrag Milanović2020-07-161-12/+14
|\ | | | | anlogic: Use dfflegalize.
| * anlogic: Use dfflegalize.Marcelina Kościelnicka2020-07-141-12/+14
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* | Revert "intel_alm: direct M10K instantiation"Lofty2020-07-131-6/+0
| | | | | | | | This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
* | xilinx: Fix srl regression.Marcelina Kościelnicka2020-07-121-0/+41
| | | | | | | | | | | | | | Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and $_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the point where xilinx_srl is called for non-abc9. Fix this by running ff_map.v first, resulting in FDRE cells, which are handled correctly.
* | gowin: Use dfflegalize.Marcelina Kościelnicka2020-07-062-13/+8
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* | intel_alm: direct M10K instantiationDan Ravensloft2020-07-051-0/+6
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* | synth_gowin: ABC9 supportDan Ravensloft2020-07-051-1/+5
| | | | | | | | | | This adds ABC9 support for synth_gowin; drastically improving synthesis quality.
* | intel_alm: add Cyclone 10 GX testsDan Ravensloft2020-07-0511-2/+236
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* | intel_alm: DSP inferenceDan Ravensloft2020-07-051-0/+23
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* | synth_intel_alm: Use dfflegalize.Marcelina Kościelnicka2020-07-041-1/+1
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* | Improve MISTRAL_FF specify rulesDan Ravensloft2020-07-041-1/+2
| | | | | | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* | tests: update fsm.ys resource countEddie Hung2020-07-041-4/+4
|/ | | | | Suspect it is to do with map/set ordering in techmap; should be fixed by #1862?
* intel_alm: fix DFFE matchingDan Ravensloft2020-06-112-4/+4
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* Add missing .gitignore fileClaire Wolf2020-06-041-0/+2
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-4/+53
|\ | | | | abc9: -dff improvements
| * abc9_ops: update messaging (credit to @Xiretza for spotting)Eddie Hung2020-05-301-4/+4
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| * tests: add test for abc9 -dff removing a redundant flop entirelyEddie Hung2020-05-251-0/+15
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| * tests: add testcase for abc9 -dff preserving flop namesEddie Hung2020-05-251-0/+34
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* | Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixesEddie Hung2020-06-031-0/+13
|\ \ | | | | | | abc9: fixes around handling combinatorial loops
| * | tests: tidy up testcaseEddie Hung2020-06-031-3/+0
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| * | tests: add ecp5 latch testcase with -abc9Eddie Hung2020-05-251-0/+16
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* | | Merge pull request #2080 from YosysHQ/eddie/fix_test_warningsEddie Hung2020-06-032-2/+2
|\ \ \ | | | | | | | | tests: reduce test warnings
| * | | tests: fix some test warningsEddie Hung2020-05-252-2/+2
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* | | allow range for mux testMiodrag Milanovic2020-06-011-1/+2
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* | tests: xilinx macc test to have initval, shorten BMC depth for runtimeEddie Hung2020-05-252-8/+8
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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-191-2/+4
| | | | Fixes #2058.
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-5/+29
| | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
* abc9: suppress warnings when no compatible + used flop boxes formedEddie Hung2020-05-141-1/+3
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* xilinx: update abc9_dff testsEddie Hung2020-05-141-18/+45
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* xilinx: remove no-longer-relevant testEddie Hung2020-05-141-91/+0
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* intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-071-0/+20
| | | | | | | | | | By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
* intel_alm: work around a Quartus ICEDan Ravensloft2020-04-231-0/+12
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* tests: read +/xilinx/cell_sim.v before xilinx_dsp testEddie Hung2020-04-221-0/+1
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* test: ice40_dsp test to read +/ice40/cells_sim.v for default paramsEddie Hung2020-04-221-0/+1
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* xilinx: xilinx_dffopt to read cells_sim.v; fix testEddie Hung2020-04-221-13/+22
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* tests: remove write_ilangEddie Hung2020-04-202-3/+0
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* synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-1510-0/+208
| | | | | | | | By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-105-35/+551
|\ | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * ecp5: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-16/+62
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| * ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-8/+28
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