| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Call equiv_opt with -multiclock and -assert | Eddie Hung | 2019-12-31 | 1 | -1/+1 |
| * | Rename memory tests to lutram, add more xilinx tests | Eddie Hung | 2019-12-12 | 1 | -3/+3 |
| * | update test | Pepijn de Vos | 2019-12-03 | 1 | -2/+3 |
| * | Use -match-init to not synth contradicting init values | Pepijn de Vos | 2019-12-03 | 1 | -10/+12 |
| * | attempt to fix formatting | Pepijn de Vos | 2019-11-25 | 1 | -138/+138 |
| * | gowin: add and test dff init values | Pepijn de Vos | 2019-11-25 | 2 | -0/+296 |
| * | gowin: Remove show command from tests. | Marcin Kościelnicki | 2019-11-22 | 1 | -1/+0 |
| * | fix fsm test with proper clock enable polarity | Pepijn de Vos | 2019-11-11 | 1 | -0/+11 |
| * | fix wide luts | Pepijn de Vos | 2019-11-06 | 1 | -7/+10 |
| * | don't cound exact luts in big muxes; futile and fragile | Pepijn de Vos | 2019-10-30 | 1 | -3/+0 |
| * | add tristate buffer and test | Pepijn de Vos | 2019-10-28 | 1 | -0/+13 |
| * | do not use wide luts in testcase | Pepijn de Vos | 2019-10-28 | 1 | -3/+3 |
| * | ALU sim tweaks | Pepijn de Vos | 2019-10-24 | 1 | -2/+2 |
| * | Add some tests | Pepijn de Vos | 2019-10-21 | 10 | -0/+224 |
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index : iCE40/yosys | |
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