gowin: add and test dff init values

2 files changed, 296 insertions, 0 deletions

diff --git a/tests/arch/gowin/init.v b/tests/arch/gowin/init.v
new file mode 100644
index 000000000..b51432d0c
--- /dev/null
+++ b/tests/arch/gowin/init.v
@@ -0,0 +1,224 @@
+module myDFF (output reg Q, input CLK, D);
+	parameter [0:0] INIT = 1'b0;
+	initial Q = INIT;
+	always @(posedge CLK)
+		Q <= D;
+endmodule
+
+module myDFFE (output reg Q, input D, CLK, CE);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(posedge CLK) begin
+    if (CE)
+      Q <= D;
+  end
+endmodule // DFFE (positive clock edge; clock enable)
+
+
+module myDFFS (output reg Q, input D, CLK, SET);
+  parameter [0:0] INIT = 1'b1;
+  initial Q = INIT;
+  always @(posedge CLK) begin
+    if (SET)
+      Q <= 1'b1;
+    else
+      Q <= D;
+  end
+endmodule // DFFS (positive clock edge; synchronous set)
+
+
+module myDFFSE (output reg Q, input D, CLK, CE, SET);
+  parameter [0:0] INIT = 1'b1;
+  initial Q = INIT;
+  always @(posedge CLK) begin
+    if (SET)
+      Q <= 1'b1;
+    else if (CE)
+      Q <= D;
+end
+endmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)
+
+
+module myDFFR (output reg Q, input D, CLK, RESET);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(posedge CLK) begin
+    if (RESET)
+      Q <= 1'b0;
+    else
+      Q <= D;
+  end
+endmodule // DFFR (positive clock edge; synchronous reset)
+
+
+module myDFFRE (output reg Q, input D, CLK, CE, RESET);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(posedge CLK) begin
+    if (RESET)
+      Q <= 1'b0;
+    else if (CE)
+      Q <= D;
+  end
+endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)
+
+
+module myDFFP (output reg Q, input D, CLK, PRESET);
+  parameter [0:0] INIT = 1'b1;
+  initial Q = INIT;
+  always @(posedge CLK or posedge PRESET) begin
+    if(PRESET)
+      Q <= 1'b1;
+    else
+      Q <= D;
+  end
+endmodule // DFFP (positive clock edge; asynchronous preset)
+
+
+module myDFFPE (output reg Q, input D, CLK, CE, PRESET);
+  parameter [0:0] INIT = 1'b1;
+  initial Q = INIT;
+  always @(posedge CLK or posedge PRESET) begin
+    if(PRESET)
+      Q <= 1'b1;
+    else if (CE)
+      Q <= D;
+  end
+endmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)
+
+
+module myDFFC (output reg Q, input D, CLK, CLEAR);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(posedge CLK or posedge CLEAR) begin
+    if(CLEAR)
+      Q <= 1'b0;
+    else
+      Q <= D;
+  end
+endmodule // DFFC (positive clock edge; asynchronous clear)
+
+
+module myDFFCE (output reg Q, input D, CLK, CE, CLEAR);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(posedge CLK or posedge CLEAR) begin
+    if(CLEAR)
+      Q <= 1'b0;
+    else if (CE)
+      Q <= D;
+  end
+endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)
+
+
+module myDFFN (output reg Q, input CLK, D);
+	parameter [0:0] INIT = 1'b0;
+	initial Q = INIT;
+	always @(negedge CLK)
+		Q <= D;
+endmodule
+
+module myDFFNE (output reg Q, input D, CLK, CE);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(negedge CLK) begin
+    if (CE)
+      Q <= D;
+  end
+endmodule // DFFNE (negative clock edge; clock enable)
+
+
+module myDFFNS (output reg Q, input D, CLK, SET);
+  parameter [0:0] INIT = 1'b1;
+  initial Q = INIT;
+  always @(negedge CLK) begin
+    if (SET)
+      Q <= 1'b1;
+    else
+      Q <= D;
+  end
+endmodule // DFFNS (negative clock edge; synchronous set)
+
+
+module myDFFNSE (output reg Q, input D, CLK, CE, SET);
+  parameter [0:0] INIT = 1'b1;
+  initial Q = INIT;
+  always @(negedge CLK) begin
+    if (SET)
+      Q <= 1'b1;
+    else if (CE)
+      Q <= D;
+end
+endmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)
+
+
+module myDFFNR (output reg Q, input D, CLK, RESET);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(negedge CLK) begin
+    if (RESET)
+      Q <= 1'b0;
+    else
+      Q <= D;
+  end
+endmodule // DFFNR (negative clock edge; synchronous reset)
+
+
+module myDFFNRE (output reg Q, input D, CLK, CE, RESET);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(negedge CLK) begin
+    if (RESET)
+      Q <= 1'b0;
+    else if (CE)
+      Q <= D;
+  end
+endmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)
+
+
+module myDFFNP (output reg Q, input D, CLK, PRESET);
+  parameter [0:0] INIT = 1'b1;
+  initial Q = INIT;
+  always @(negedge CLK or posedge PRESET) begin
+    if(PRESET)
+      Q <= 1'b1;
+    else
+      Q <= D;
+  end
+endmodule // DFFNP (negative clock edge; asynchronous preset)
+
+
+module myDFFNPE (output reg Q, input D, CLK, CE, PRESET);
+  parameter [0:0] INIT = 1'b1;
+  initial Q = INIT;
+  always @(negedge CLK or posedge PRESET) begin
+    if(PRESET)
+      Q <= 1'b1;
+    else if (CE)
+      Q <= D;
+  end
+endmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)
+
+
+module myDFFNC (output reg Q, input D, CLK, CLEAR);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(negedge CLK or posedge CLEAR) begin
+    if(CLEAR)
+      Q <= 1'b0;
+    else
+      Q <= D;
+  end
+endmodule // DFFNC (negative clock edge; asynchronous clear)
+
+
+module myDFFNCE (output reg Q, input D, CLK, CE, CLEAR);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(negedge CLK or posedge CLEAR) begin
+    if(CLEAR)
+      Q <= 1'b0;
+    else if (CE)
+      Q <= D;
+  end
+endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)
diff --git a/tests/arch/gowin/init.ys b/tests/arch/gowin/init.ys
new file mode 100644
index 000000000..dc8206825
--- /dev/null
+++ b/tests/arch/gowin/init.ys
@@ -0,0 +1,72 @@
+read_verilog init.v
+read_verilog -lib +/gowin/cells_sim.v
+design -save read
+
+proc
+flatten
+synth_gowin -run coarse:
+
+# check if all init values are handled
+check -assert -noinit
+# check if every flop mapped correctly
+select -assert-count 1 t:DFF
+select -assert-count 1 t:DFFC
+select -assert-count 1 t:DFFCE
+select -assert-count 1 t:DFFE
+select -assert-count 1 t:DFFN
+select -assert-count 1 t:DFFNC
+select -assert-count 1 t:DFFNCE
+select -assert-count 1 t:DFFNE
+select -assert-count 1 t:DFFNP
+select -assert-count 1 t:DFFNPE
+select -assert-count 1 t:DFFNR
+select -assert-count 1 t:DFFNRE
+select -assert-count 1 t:DFFNS
+select -assert-count 1 t:DFFNSE
+select -assert-count 1 t:DFFP
+select -assert-count 1 t:DFFPE
+select -assert-count 1 t:DFFR
+select -assert-count 1 t:DFFRE
+select -assert-count 1 t:DFFS
+select -assert-count 1 t:DFFSE
+
+delete
+design -load read
+
+# these should synth to a flop with reset
+chparam -set INIT 1 myDFF myDFFN myDFFE myDFFNE
+
+# these should give a warning
+chparam -set INIT 0 myDFF*S* myDFF*P*
+chparam -set INIT 1 myDFF*R* myDFF*C*
+
+proc
+flatten
+synth_gowin -run coarse:
+
+# check the flops mapped as expected
+select -assert-count 0 t:DFF
+select -assert-count 1 t:DFFC
+select -assert-count 1 t:DFFCE
+select -assert-count 0 t:DFFE
+select -assert-count 0 t:DFFN
+select -assert-count 1 t:DFFNC
+select -assert-count 1 t:DFFNCE
+select -assert-count 0 t:DFFNE
+select -assert-count 1 t:DFFNP
+select -assert-count 1 t:DFFNPE
+select -assert-count 1 t:DFFNR
+select -assert-count 1 t:DFFNRE
+select -assert-count 2 t:DFFNS
+select -assert-count 2 t:DFFNSE
+select -assert-count 1 t:DFFP
+select -assert-count 1 t:DFFPE
+select -assert-count 1 t:DFFR
+select -assert-count 1 t:DFFRE
+select -assert-count 2 t:DFFS
+select -assert-count 2 t:DFFSE
+
+# check the expected leftover init values
+# this would happen if your reset value is not the initial value
+# which would be weird
+select -assert-count 16 a:init