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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-11-11 17:51:26 +0100 |
|---|---|---|
| committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-11-11 17:51:26 +0100 |
| commit | ab8c521030a2c91a1e388d6f3c627a7f7dd525b2 (patch) | |
| tree | d48eb9f4b093113008d46a5bf2dc004d7143a943 /tests/arch/gowin | |
| parent | ec3faa7b967564dabdd465267657def86846b259 (diff) | |
| download | yosys-ab8c521030a2c91a1e388d6f3c627a7f7dd525b2.tar.gz yosys-ab8c521030a2c91a1e388d6f3c627a7f7dd525b2.tar.bz2 yosys-ab8c521030a2c91a1e388d6f3c627a7f7dd525b2.zip | |
fix fsm test with proper clock enable polarity
Diffstat (limited to 'tests/arch/gowin')
| -rw-r--r-- | tests/arch/gowin/fsm.ys | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/arch/gowin/fsm.ys b/tests/arch/gowin/fsm.ys new file mode 100644 index 000000000..ce4504522 --- /dev/null +++ b/tests/arch/gowin/fsm.ys @@ -0,0 +1,11 @@ +read_verilog ../common/fsm.v +hierarchy -top fsm +proc +flatten + +equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin # equivalency check +miter -equiv -make_assert -flatten gold gate miter +sat -verify -show-all -dump_vcd x.vcd -prove-asserts -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + +#design -load postopt +#shell |