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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-24 13:39:43 +0200 |
|---|---|---|
| committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-24 13:39:43 +0200 |
| commit | 8226f2db0b65dffb59c4420de96dccd2e0be36ed (patch) | |
| tree | d4ae8d996ea87c741b454c7609d8b1b9fe5424c6 /tests/arch/gowin | |
| parent | 83fbfe0964dc7315ca6d508e6069507250d9f093 (diff) | |
| download | yosys-8226f2db0b65dffb59c4420de96dccd2e0be36ed.tar.gz yosys-8226f2db0b65dffb59c4420de96dccd2e0be36ed.tar.bz2 yosys-8226f2db0b65dffb59c4420de96dccd2e0be36ed.zip | |
ALU sim tweaks
Diffstat (limited to 'tests/arch/gowin')
| -rw-r--r-- | tests/arch/gowin/mux.ys | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys index c9c85019b..d612e4eaa 100644 --- a/tests/arch/gowin/mux.ys +++ b/tests/arch/gowin/mux.ys @@ -42,8 +42,8 @@ proc equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 9 t:LUT4 -select -assert-count 3 t:LUT3 +select -assert-count 10 t:LUT4 +select -assert-count 1 t:LUT3 select -assert-count 20 t:IBUF select -assert-count 1 t:OBUF |