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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-28 14:40:12 +0100 |
|---|---|---|
| committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-28 14:40:12 +0100 |
| commit | 9517525224c7bc4b8ac7d093066485888a337b76 (patch) | |
| tree | 6dd3f81a447565eb4fbcdecaaf52ab0fcd09437b /tests/arch/gowin | |
| parent | 4ec4d5ec7e6c70c50c513de93c1d478ff76d8298 (diff) | |
| download | yosys-9517525224c7bc4b8ac7d093066485888a337b76.tar.gz yosys-9517525224c7bc4b8ac7d093066485888a337b76.tar.bz2 yosys-9517525224c7bc4b8ac7d093066485888a337b76.zip | |
do not use wide luts in testcase
Diffstat (limited to 'tests/arch/gowin')
| -rw-r--r-- | tests/arch/gowin/mux.ys | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys index d612e4eaa..1cb3d53e6 100644 --- a/tests/arch/gowin/mux.ys +++ b/tests/arch/gowin/mux.ys @@ -15,7 +15,7 @@ select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D design -load read hierarchy -top mux4 proc -equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module select -assert-count 2 t:LUT4 @@ -27,7 +27,7 @@ select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D design -load read hierarchy -top mux8 proc -equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module select -assert-count 5 t:LUT4 @@ -39,7 +39,7 @@ select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D design -load read hierarchy -top mux16 proc -equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-count 10 t:LUT4 |