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* Fix spacingEddie Hung2020-01-021-1/+1
* synth_xilinx -dff to work with abc tooEddie Hung2020-01-021-6/+14
* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-0214-66/+86
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| * Merge pull request #1601 from YosysHQ/eddie/synth_retimeEddie Hung2020-01-0212-37/+37
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| | * Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-3011-12/+12
| | * Disable synth_gowin -abc9 as it offers no advantages yetEddie Hung2019-12-301-12/+12
| | * Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-3011-13/+13
| * | ifdef __ICARUS__ -> ifndef YOSYSEddie Hung2020-01-011-6/+6
| * | Fix anlogic async flop mappingEddie Hung2020-01-011-8/+8
| * | Update timings for Xilinx S7 cellsEddie Hung2019-12-301-15/+35
* | | Update commentsEddie Hung2020-01-021-11/+6
* | | abc9 -keepff -> -dff; refactor dff operationsEddie Hung2020-01-022-58/+58
* | | Clamp -46ps for FDPE* tooEddie Hung2020-01-011-2/+2
* | | Restore abc9 -keepffEddie Hung2020-01-012-86/+6
* | | Re-arrange FD orderEddie Hung2019-12-313-182/+182
* | | Missing characterEddie Hung2019-12-311-1/+1
* | | Cleanup xilinx boxesEddie Hung2019-12-312-391/+425
* | | Cleanup ice40 boxesEddie Hung2019-12-313-30/+43
* | | Cleanup ecp5 boxesEddie Hung2019-12-314-35/+31
* | | Update abc9_xc7.box commentsEddie Hung2019-12-311-18/+18
* | | FDCE ports to be alphabeticalEddie Hung2019-12-311-3/+3
* | | Fix attributes on $__ABC9_ASYNC[01] whiteboxEddie Hung2019-12-311-2/+2
* | | Fix incorrect $__ABC9_ASYNC[01] boxEddie Hung2019-12-311-2/+2
* | | Do not offset FD* box timings due to -46ps TsuEddie Hung2019-12-301-12/+21
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-3010-32/+377
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| * | Merge pull request #1589 from YosysHQ/iopad_defaultMiodrag Milanović2019-12-301-11/+6
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| | * Merge remote-tracking branch 'origin/master' into iopad_defaultMiodrag Milanovic2019-12-288-10/+368
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| | * | Addressed review commentsMiodrag Milanovic2019-12-211-2/+3
| | * | iopad no op for compatibility with old scriptsMiodrag Milanovic2019-12-211-0/+3
| | * | Make iopad option default for all xilinx flowsMiodrag Milanovic2019-12-211-14/+5
| * | | Nitpick cleanup for ecp5Eddie Hung2019-12-272-11/+3
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| * | Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgenMarcin Kościelnicki2019-12-253-3/+6
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| | * | xilinx_dsp: Initial DSP48A/DSP48A1 support.Marcin Kościelnicki2019-12-223-3/+6
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| * / xilinx: Test our DSP48A/DSP48A1 simulation models.Marcin Kościelnicki2019-12-235-7/+362
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* | Tidy up abc9_map.vEddie Hung2019-12-301-103/+103
* | Add "synth_xilinx -dff" option, cleanup abc9Eddie Hung2019-12-302-2/+98
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-24/+10
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| * Add abc9_arrival times for RAM{32,64}MEddie Hung2019-12-201-24/+10
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-204-172/+240
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| * Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-201-0/+78
| * Revert "Optimise write_xaiger"Eddie Hung2019-12-203-15/+0
| * Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-193-0/+15
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| | * techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-063-0/+15
| * | xilinx: Add simulation models for remaining CLB primitives.Marcin Kościelnicki2019-12-193-156/+210
| * | xilinx_dffopt: Keep order of LUT inputs.Marcin Kościelnicki2019-12-191-16/+30
* | | Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-191-0/+78
* | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-195-36/+55
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1914-81/+995
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| * | Merge pull request #1563 from YosysHQ/dave/async-prldDavid Shah2019-12-182-4/+28
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| | * | ecp5: Add support for mapping PRLD FFsDavid Shah2019-12-072-4/+28
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