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| author | Marcin Kościelnicki <mwk@0x04.net> | 2019-12-25 16:18:44 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-25 16:18:44 +0100 |
| commit | 13a3041030d9475fdb45dd650f62aaa9dc8bb876 (patch) | |
| tree | 0ef54d1c4b970df2ba6766977525368a5d0a9977 /techlibs | |
| parent | dadaf7ed788370c94a463e5e479bed4d540cdf4b (diff) | |
| parent | e226a8f7f1e2fa55102890462fc2a0097a04092b (diff) | |
| download | yosys-13a3041030d9475fdb45dd650f62aaa9dc8bb876.tar.gz yosys-13a3041030d9475fdb45dd650f62aaa9dc8bb876.tar.bz2 yosys-13a3041030d9475fdb45dd650f62aaa9dc8bb876.zip | |
Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen
xilinx_dsp: Initial DSP48A/DSP48A1 support.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 5 | ||||
| -rw-r--r-- | techlibs/xilinx/xc3sda_dsp_map.v | 2 | ||||
| -rw-r--r-- | techlibs/xilinx/xc6s_dsp_map.v | 2 |
3 files changed, 6 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 971089b28..a19046911 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -387,7 +387,10 @@ struct SynthXilinxPass : public ScriptPass run("opt_expr -fine"); run("wreduce"); run("select -clear"); - run("xilinx_dsp"); + if (help_mode) + run("xilinx_dsp -family <family>"); + else + run("xilinx_dsp -family " + family); run("chtype -set $mul t:$__soft_mul"); } } diff --git a/techlibs/xilinx/xc3sda_dsp_map.v b/techlibs/xilinx/xc3sda_dsp_map.v index 87348a173..258f90395 100644 --- a/techlibs/xilinx/xc3sda_dsp_map.v +++ b/techlibs/xilinx/xc3sda_dsp_map.v @@ -27,7 +27,7 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); .D(18'b0), .P(P_48), - .OPMODE(8'b0000010) + .OPMODE(8'b0000001) ); assign Y = P_48; endmodule diff --git a/techlibs/xilinx/xc6s_dsp_map.v b/techlibs/xilinx/xc6s_dsp_map.v index e8705723b..bdce60c14 100644 --- a/techlibs/xilinx/xc6s_dsp_map.v +++ b/techlibs/xilinx/xc6s_dsp_map.v @@ -27,7 +27,7 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); .D(18'b0), .P(P_48), - .OPMODE(8'b0000010) + .OPMODE(8'b0000001) ); assign Y = P_48; endmodule |