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authorEddie Hung <eddie@fpgeh.com>2019-12-31 18:29:37 -0800
committerEddie Hung <eddie@fpgeh.com>2019-12-31 18:29:37 -0800
commit2358320f5168edd691882bba0f759d82308291d6 (patch)
tree13969f24cfa0003abf7da17b9180ca114cf2d123 /techlibs
parentb2046a2114add3d24c0affd9d885b7ee320dba27 (diff)
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Cleanup ice40 boxes
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/ice40/abc9_hx.box24
-rw-r--r--techlibs/ice40/abc9_lp.box24
-rw-r--r--techlibs/ice40/abc9_u.box25
3 files changed, 43 insertions, 30 deletions
diff --git a/techlibs/ice40/abc9_hx.box b/techlibs/ice40/abc9_hx.box
index 3ea70bc91..31e743669 100644
--- a/techlibs/ice40/abc9_hx.box
+++ b/techlibs/ice40/abc9_hx.box
@@ -1,13 +1,17 @@
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
-# NB: Inputs/Outputs must be ordered alphabetically
-# (with exceptions for carry in/out)
+# NB: Box inputs/outputs must each be in the same order
+# as their corresponding module definition
+# (with exceptions detailed below)
-# Inputs: A B I0 I3 CI
-# Outputs: O CO
-# (NB: carry chain input/output must be last
-# input/output and have been moved there
-# overriding the alphabetical ordering)
-$__ICE40_CARRY_WRAPPER 1 1 5 2
-400 379 449 316 316
-259 231 - - 126
+# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
+# SB_LUT4+SB_CARRY)
+# (Exception: carry chain input/output must be the
+# last input and output and the entire bus has been
+# moved there overriding the otherwise
+# alphabetical ordering)
+# name ID w/b ins outs
+$__ICE40_CARRY_WRAPPER 1 1 5 2
+#A B I0 I3 CI
+400 379 449 316 316 # O
+259 231 - - 126 # CO
diff --git a/techlibs/ice40/abc9_lp.box b/techlibs/ice40/abc9_lp.box
index 473e92fe9..71986a67b 100644
--- a/techlibs/ice40/abc9_lp.box
+++ b/techlibs/ice40/abc9_lp.box
@@ -1,13 +1,17 @@
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
-# NB: Inputs/Outputs must be ordered alphabetically
-# (with exceptions for carry in/out)
+# NB: Box inputs/outputs must each be in the same order
+# as their corresponding module definition
+# (with exceptions detailed below)
-# Inputs: A B I0 I3 CI
-# Outputs: O CO
-# (NB: carry chain input/output must be last
-# input/output and have been moved there
-# overriding the alphabetical ordering)
-$__ICE40_CARRY_WRAPPER 1 1 5 2
-589 558 661 465 465
-675 609 - - 186
+# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
+# SB_LUT4+SB_CARRY)
+# (Exception: carry chain input/output must be the
+# last input and output and the entire bus has been
+# moved there overriding the otherwise
+# alphabetical ordering)
+# name ID w/b ins outs
+$__ICE40_CARRY_WRAPPER 1 1 5 2
+#A B I0 I3 CI
+589 558 661 465 465 # O
+675 609 - - 186 # CO
diff --git a/techlibs/ice40/abc9_u.box b/techlibs/ice40/abc9_u.box
index f00e247b8..48a51463e 100644
--- a/techlibs/ice40/abc9_u.box
+++ b/techlibs/ice40/abc9_u.box
@@ -1,13 +1,18 @@
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
-# NB: Inputs/Outputs must be ordered alphabetically
-# (with exceptions for carry in/out)
+# NB: Box inputs/outputs must each be in the same order
+# as their corresponding module definition
+# (with exceptions detailed below)
-# Inputs: A B I0 I3 CI
-# Outputs: O CO
-# (NB: carry chain input/output must be last
-# input/output and have been moved there
-# overriding the alphabetical ordering)
-$__ICE40_CARRY_WRAPPER 1 1 5 2
-1231 1205 1285 874 874
-675 609 - - 278
+# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
+# SB_LUT4+SB_CARRY)
+# Outputs: O, CO
+# (Exception: carry chain input/output must be the
+# last input and output and the entire bus has been
+# moved there overriding the otherwise
+# alphabetical ordering)
+# name ID w/b ins outs
+$__ICE40_CARRY_WRAPPER 1 1 5 2
+#A B I0 I3 CI
+1231 1205 1285 874 874 # O
+675 609 - - 278 # CO