Restore abc9 -keepff

2 files changed, 6 insertions, 86 deletions

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 6d93e508f..1b58c34c0 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -21,7 +21,8 @@
 // The following techmapping rules are intended to be run (with -max_iter 1)
 //   before invoking the `abc9` pass in order to transform the design into
 //   a format that it understands.
-//
+
+`ifdef DFF_MODE
 // For example, (complex) flip-flops are expected to be described as an
 //   combinatorial box (containing all control logic such as clock enable
 //   or synchronous resets) followed by a basic D-Q flop.
@@ -83,7 +84,6 @@ module FDRE (output Q, input C, CE, D, R);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
-`ifdef DFF_MODE
   wire QQ, $Q;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -114,21 +114,9 @@ module FDRE (output Q, input C, CE, D, R);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
-`else
-  (* abc9_keep *)
-  FDRE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_R_INVERTED(IS_R_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
-  );
-`endif
 endmodule
 module FDRE_1 (output Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
-`ifdef DFF_MODE
   wire QQ, $Q;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -153,14 +141,6 @@ module FDRE_1 (output Q, input C, CE, D, R);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
-`else
-  (* abc9_keep *)
-  FDRE_1 #(
-    .INIT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
-  );
-`endif
 endmodule
 
 module FDSE (output Q, input C, CE, D, S);
@@ -168,7 +148,6 @@ module FDSE (output Q, input C, CE, D, S);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
-`ifdef DFF_MODE
   wire QQ, $Q;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -198,21 +177,9 @@ module FDSE (output Q, input C, CE, D, S);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
-`else
-  (* abc9_keep *)
-  FDSE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_S_INVERTED(IS_S_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .S(S)
-  );
-`endif
 endmodule
 module FDSE_1 (output Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
-`ifdef DFF_MODE
   wire QQ, $Q;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -236,14 +203,6 @@ module FDSE_1 (output Q, input C, CE, D, S);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
-`else
-  (* abc9_keep *)
-  FDSE_1 #(
-    .INIT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .S(S)
-  );
-`endif
 endmodule
 
 module FDCE (output Q, input C, CE, D, CLR);
@@ -251,7 +210,6 @@ module FDCE (output Q, input C, CE, D, CLR);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
-`ifdef DFF_MODE
   wire QQ, $Q, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -295,21 +253,9 @@ module FDCE (output Q, input C, CE, D, CLR);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
-`else
-  (* abc9_keep *)
-  FDCE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_CLR_INVERTED(IS_CLR_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
-  );
-`endif
 endmodule
 module FDCE_1 (output Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
-`ifdef DFF_MODE
   wire QQ, $Q, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -345,14 +291,6 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
-`else
-  (* abc9_keep *)
-  FDCE_1 #(
-    .INIT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
-  );
-`endif
 endmodule
 
 module FDPE (output Q, input C, CE, D, PRE);
@@ -360,7 +298,6 @@ module FDPE (output Q, input C, CE, D, PRE);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
-`ifdef DFF_MODE
   wire QQ, $Q, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -402,21 +339,9 @@ module FDPE (output Q, input C, CE, D, PRE);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
-`else
-  (* abc9_keep *)
-  FDPE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_PRE_INVERTED(IS_PRE_INVERTED),
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
-  );
-`endif
 endmodule
 module FDPE_1 (output Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
-`ifdef DFF_MODE
   wire QQ, $Q, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -452,15 +377,8 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
-`else
-  (* abc9_keep *)
-  FDPE_1 #(
-    .INIT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
-  );
-`endif
 endmodule
+`endif
 
 // Attach a (combinatorial) black-box onto the output
 //   of thes LUTRAM primitives to capture their
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index f2a9ae982..10aa7be5f 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -108,7 +108,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("        flatten design before synthesis\n");
 		log("\n");
 		log("    -dff\n");
-		log("        run 'abc9' with -dff option\n");
+		log("        enable sequential synthesis with 'abc9'\n");
 		log("\n");
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
@@ -559,6 +559,8 @@ struct SynthXilinxPass : public ScriptPass
 					abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
 				else
 					abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
+				if (!dff_mode)
+					abc9_opts += " -keepff";
 				run("abc9" + abc9_opts);
 				run("techmap -map +/xilinx/abc9_unmap.v");
 			}