aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
diff options
context:
space:
mode:
authorEddie Hung <eddie@fpgeh.com>2020-01-02 12:39:52 -0800
committerEddie Hung <eddie@fpgeh.com>2020-01-02 12:39:52 -0800
commitec1756c0941fac02614c25307b17bb41fe36f468 (patch)
tree35c19b2ce32ed2632ff53fde17b30ce0b1216c92 /techlibs
parent8e507bd80785db9fa6723eada4214a5a06516cae (diff)
downloadyosys-ec1756c0941fac02614c25307b17bb41fe36f468.tar.gz
yosys-ec1756c0941fac02614c25307b17bb41fe36f468.tar.bz2
yosys-ec1756c0941fac02614c25307b17bb41fe36f468.zip
Update comments
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/xilinx/abc9_map.v17
1 files changed, 6 insertions, 11 deletions
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 1d37952f5..af58e217c 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -65,19 +65,14 @@
// the connectivity of its basic D-Q flop
// (b) an optional $__ABC9_ASYNC_ cell in front of $__ABC_FF_'s output to
// capture asynchronous behaviour
-// (c) a special _TECHMAP_REPLACE_.abc9_ff.clock wire to capture its clock
-// domain and polarity (used when partitioning the module so that `abc9' only
-// performs sequential synthesis (with reachability analysis) correctly on
-// one domain at a time) and also used to infer the optional delay target
-// from the (* abc9_clock_period = %d *) attribute attached to any wire
-// within
-// (d) a special _TECHMAP_REPLACE_.abc9_ff.init wire to encode the flop's initial
-// state
+// (c) a special abc9_ff.clock wire to capture its clock domain and polarity
+// (indicated to `abc9' so that it only performs sequential synthesis
+// (with reachability analysis) correctly on one domain at a time)
+// (d) a special abc9_ff.init wire to encode the flop's initial state
+// NOTE: in order to perform sequential synthesis, `abc9' also requires
+// that the initial value of all flops be zero
// (e) a special _TECHMAP_REPLACE_.abc9_ff.Q wire that will be used for feedback
// into the (combinatorial) FD* cell to facilitate clock-enable behaviour
-//
-// In order to perform sequential synthesis, `abc9' also requires that
-// the initial value of all flops be zero.
module FDRE (output Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;