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* Xilinx RAMB36/RAMB18 memory_bram support completeClifford Wolf2015-01-063-16/+320
* Towards Xilinx bram supportClifford Wolf2015-01-063-24/+65
* small fix in xilinx/brams.vClifford Wolf2015-01-061-5/+5
* Towards Xilinx bram supportClifford Wolf2015-01-064-25/+176
* Various small improvements to synth_xilinxClifford Wolf2015-01-061-8/+6
* Towards Xilinx bram supportClifford Wolf2015-01-062-13/+41
* Towards Xilinx bram supportClifford Wolf2015-01-063-6/+10
* Towards Xilinx bram supportClifford Wolf2015-01-057-19/+172
* Towards Xilinx bram supportClifford Wolf2015-01-043-13/+182
* Progress in memory_bramClifford Wolf2015-01-031-0/+3
* Added proper clkpol support to memory_bramClifford Wolf2015-01-021-1/+1
* New $mem simlib modelClifford Wolf2015-01-021-95/+36
* Progress in memory_bramClifford Wolf2014-12-311-3/+3
* Added memory_bram (not functional yet)Clifford Wolf2014-12-311-0/+20
* Fixed simlib entries for $memrd and $memwrClifford Wolf2014-12-301-0/+2
* Fixed build with SMALL=1Clifford Wolf2014-12-301-0/+2
* Improvements in simplemap api, added $ne $nex $eq $eqx supportClifford Wolf2014-12-241-49/+5
* Removed UTF-8 chars from techmap.vClifford Wolf2014-12-121-1/+1
* Added $dffe cell typeClifford Wolf2014-12-082-1/+20
* Added $_DFFE_??_ cell typesClifford Wolf2014-12-081-0/+32
* Added "abc" label in synth scriptClifford Wolf2014-10-311-6/+12
* Added "opt -full" alias for all more aggressive optimizationsClifford Wolf2014-10-311-2/+6
* Added $_BUF_ cell typeClifford Wolf2014-10-031-0/+6
* namespace YosysClifford Wolf2014-09-272-2/+10
* Improvements in "synth" scriptClifford Wolf2014-09-181-8/+12
* Fixed $macc simlib model for zero-configClifford Wolf2014-09-161-1/+1
* Added "synth" commandClifford Wolf2014-09-142-0/+154
* Using alumacc in techmap.vClifford Wolf2014-09-141-237/+33
* Fixed simlib $macc model for xilinx xsimClifford Wolf2014-09-081-1/+15
* Simplified $fa undef modelClifford Wolf2014-09-081-1/+1
* Fixes and cleanups for blackbox.vClifford Wolf2014-09-082-70/+73
* Added $lcu cell typeClifford Wolf2014-09-082-74/+31
* Added "$fa" cell typeClifford Wolf2014-09-082-0/+28
* Using maccmap for $macc and $mul techmapClifford Wolf2014-09-071-190/+16
* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-062-2/+2
* Added $macc SAT modelClifford Wolf2014-09-062-6/+6
* Added $macc simlib model (also use as techmap rule for now)Clifford Wolf2014-09-062-0/+172
* Removed $bu0 cell typeClifford Wolf2014-09-042-34/+5
* Undef-related fixes in simlib $alu modelClifford Wolf2014-09-021-3/+6
* Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-021-3/+2
* Fixed "test_cell -simlib all"Clifford Wolf2014-09-011-2/+3
* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-311-0/+17
* Added $alu cell typeClifford Wolf2014-08-302-3/+47
* Replaced $__alu CO/CS outputs with full-width CO outputClifford Wolf2014-08-301-32/+28
* Using "via_celltype" in $mul carry-save-acc implementationClifford Wolf2014-08-181-34/+72
* Performance fix for new $__lcu techmap ruleClifford Wolf2014-08-181-7/+5
* Replaced recursive lcu scheme with bk adderClifford Wolf2014-08-181-61/+31
* Multiply using a carry-save accumulatorClifford Wolf2014-08-161-5/+45
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-161-0/+42
* Changes in techmap $__alu interfaceClifford Wolf2014-08-161-17/+17
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