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| author | Clifford Wolf <clifford@clifford.at> | 2014-09-08 16:59:39 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-08 16:59:39 +0200 |
| commit | fcb46138cebd57587d35489cef3a3a48ebe40bcf (patch) | |
| tree | 017526971d972de1ad8d17e4b0e2dd567e038007 /techlibs | |
| parent | 6dc07eb1f23757b17b6d856c95d0901d751eeb25 (diff) | |
| download | yosys-fcb46138cebd57587d35489cef3a3a48ebe40bcf.tar.gz yosys-fcb46138cebd57587d35489cef3a3a48ebe40bcf.tar.bz2 yosys-fcb46138cebd57587d35489cef3a3a48ebe40bcf.zip | |
Simplified $fa undef model
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index da745b5e0..dd12bd39f 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -453,7 +453,7 @@ output [WIDTH-1:0] X, Y; wire [WIDTH-1:0] t1, t2, t3; assign t1 = A ^ B, t2 = A & B, t3 = C & t1; -assign Y = t1 ^ C, X = t2 | t3; +assign Y = t1 ^ C, X = (t2 | t3) ^ (Y ^ Y); endmodule |