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| author | Clifford Wolf <clifford@clifford.at> | 2014-12-30 13:33:29 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-30 13:33:29 +0100 |
| commit | ba43cf5807dadac970ff10afed4963d1ee329217 (patch) | |
| tree | 34604cd04b7039544795eb87b985867ff7a4adcc /techlibs | |
| parent | 120a8313d915c2ebac43c8bf0b8216b240e769c1 (diff) | |
| download | yosys-ba43cf5807dadac970ff10afed4963d1ee329217.tar.gz yosys-ba43cf5807dadac970ff10afed4963d1ee329217.tar.bz2 yosys-ba43cf5807dadac970ff10afed4963d1ee329217.zip | |
Fixed simlib entries for $memrd and $memwr
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index e241cd3ce..bacf4a17e 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1449,6 +1449,7 @@ parameter WIDTH = 8; parameter CLK_ENABLE = 0; parameter CLK_POLARITY = 0; +parameter TRANSPARENT = 0; input CLK; input [ABITS-1:0] ADDR; @@ -1473,6 +1474,7 @@ parameter WIDTH = 8; parameter CLK_ENABLE = 0; parameter CLK_POLARITY = 0; +parameter PRIORITY = 0; input CLK; input [WIDTH-1:0] EN; |