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| author | Clifford Wolf <clifford@clifford.at> | 2014-09-01 15:37:56 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-01 15:37:56 +0200 |
| commit | 9923762461d2bc0822daef76bf0b58e772045bc8 (patch) | |
| tree | 0db9454dd1afc6f81f5325075977f0fc57ef26f1 /techlibs | |
| parent | c7f81e4e49b3c2be1280cd0895170a5d89d9c444 (diff) | |
| download | yosys-9923762461d2bc0822daef76bf0b58e772045bc8.tar.gz yosys-9923762461d2bc0822daef76bf0b58e772045bc8.tar.bz2 yosys-9923762461d2bc0822daef76bf0b58e772045bc8.zip | |
Fixed "test_cell -simlib all"
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 09ffa9a68..3c931c813 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -108,12 +108,13 @@ parameter Y_WIDTH = 0; input [A_WIDTH-1:0] A; output [Y_WIDTH-1:0] Y; +wire [Y_WIDTH-1:0] tmp; generate if (A_SIGNED) begin:BLOCK1 - assign Y = -$signed(A); + assign tmp = $signed(A), Y = -tmp; end else begin:BLOCK2 - assign Y = -A; + assign tmp = A, Y = -tmp; end endgenerate |