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| author | Clifford Wolf <clifford@clifford.at> | 2014-10-31 03:36:51 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-10-31 03:36:51 +0100 |
| commit | ab28491f271e3b02ba58dabb4b7033bcf17b6c25 (patch) | |
| tree | a8fe074a05d66477549338934259f6f80eed7fa4 /techlibs | |
| parent | a21481b338933f9498fd0fb11492aa2e5b7a00cd (diff) | |
| download | yosys-ab28491f271e3b02ba58dabb4b7033bcf17b6c25.tar.gz yosys-ab28491f271e3b02ba58dabb4b7033bcf17b6c25.tar.bz2 yosys-ab28491f271e3b02ba58dabb4b7033bcf17b6c25.zip | |
Added "opt -full" alias for all more aggressive optimizations
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/synth.cc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 8b41a003d..c76b002cc 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -76,9 +76,11 @@ struct SynthPass : public Pass { log(" opt_clean\n"); log("\n"); log(" fine:\n"); + log(" opt -fast -full\n"); log(" memory_map\n"); + log(" opt -full\n"); log(" techmap\n"); - log(" opt -fast\n"); + log(" opt -fast -full\n"); #ifdef YOSYS_ENABLE_ABC log(" abc -fast\n"); log(" opt_clean\n"); @@ -144,9 +146,11 @@ struct SynthPass : public Pass { if (check_label(active, run_from, run_to, "fine")) { + Pass::call(design, "opt -fast -full"); Pass::call(design, "memory_map"); + Pass::call(design, "opt -full"); Pass::call(design, "techmap"); - Pass::call(design, "opt -fast"); + Pass::call(design, "opt -fast -full"); #ifdef YOSYS_ENABLE_ABC Pass::call(design, "abc -fast"); Pass::call(design, "opt_clean"); |