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| author | Clifford Wolf <clifford@clifford.at> | 2014-09-04 02:07:52 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-04 02:07:52 +0200 |
| commit | 8927aa6148f5575b2da9bfb76afb4af076fe18f3 (patch) | |
| tree | 4da0980333589d4785880e48383c6f44e4a94887 /techlibs | |
| parent | b9cb483f3e2a498ee75a422e09164a920918362b (diff) | |
| download | yosys-8927aa6148f5575b2da9bfb76afb4af076fe18f3.tar.gz yosys-8927aa6148f5575b2da9bfb76afb4af076fe18f3.tar.bz2 yosys-8927aa6148f5575b2da9bfb76afb4af076fe18f3.zip | |
Removed $bu0 cell type
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 24 | ||||
| -rw-r--r-- | techlibs/common/techmap.v | 15 |
2 files changed, 5 insertions, 34 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 61215f59e..17700a61e 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -55,30 +55,6 @@ endmodule // -------------------------------------------------------- -module \$bu0 (A, Y); - -parameter A_SIGNED = 0; -parameter A_WIDTH = 0; -parameter Y_WIDTH = 0; - -input [A_WIDTH-1:0] A; -output [Y_WIDTH-1:0] Y; - -generate - if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:BLOCK1 - assign Y[A_WIDTH-1:0] = A; - assign Y[Y_WIDTH-1:A_WIDTH] = 0; - end else if (A_SIGNED) begin:BLOCK2 - assign Y = $signed(A); - end else begin:BLOCK3 - assign Y = A; - end -endgenerate - -endmodule - -// -------------------------------------------------------- - module \$pos (A, Y); parameter A_SIGNED = 0; diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index c0645267d..fccbe2f81 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -39,11 +39,6 @@ // -------------------------------------------------------- (* techmap_simplemap *) -(* techmap_celltype = "$pos $bu0" *) -module simplemap_buffers; -endmodule - -(* techmap_simplemap *) (* techmap_celltype = "$not $and $or $xor $xnor" *) module simplemap_bool_ops; endmodule @@ -59,7 +54,7 @@ module simplemap_logic_ops; endmodule (* techmap_simplemap *) -(* techmap_celltype = "$slice $concat $mux" *) +(* techmap_celltype = "$pos $slice $concat $mux" *) module simplemap_various; endmodule @@ -738,8 +733,8 @@ module \$eq (A, B, Y); wire carry, carry_sign; wire [WIDTH-1:0] A_buf, B_buf; - \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf)); - \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf)); + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf)); assign Y = ~|(A_buf ^ B_buf); endmodule @@ -759,8 +754,8 @@ module \$ne (A, B, Y); wire carry, carry_sign; wire [WIDTH-1:0] A_buf, B_buf; - \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf)); - \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf)); + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf)); assign Y = |(A_buf ^ B_buf); endmodule |