aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
Commit message (Expand)AuthorAgeFilesLines
* Merge pull request #3630 from yrabbit/gw1n4c-pllMiodrag Milanović2023-01-181-0/+47
|\
| * gowin: add a new type of PLL - PLLVRYRabbit2023-01-111-0/+47
* | Merge pull request #3537 from jix/xpropJannis Harder2023-01-112-10/+60
|\ \ | |/ |/|
| * Add bitwise `$bweqx` and `$bwmux` cellsJannis Harder2022-11-302-1/+38
| * simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signalJannis Harder2022-11-301-2/+8
| * simlib: Silence iverilog warning for `$lut`Jannis Harder2022-11-301-1/+1
| * simlib: Fix wide $bmux and avoid iverilog warningsJannis Harder2022-11-301-2/+2
| * satgen, simlib: Consistent x-propagation for `$pmux` cellsJannis Harder2022-11-301-4/+11
* | nexus: Fix BRAM write enable in PDP modegatecat2023-01-041-2/+2
|/
* fabulous: Allow adding extra custom prims and map rulesgatecat2022-11-171-0/+32
* fabulous: improvements to the passgatecat2022-11-176-139/+199
* fabulous: Unify and update primitivesgatecat2022-11-173-852/+356
* Introduce RegFile mappingsTaoBi222022-11-174-2/+95
* Replace synth call with components, reintroduce flags and correct vpr flag im...TaoBi222022-11-171-4/+76
* Reorder operations to load in primitive library before hierarchy passTaoBi222022-11-171-5/+6
* Add plib flag to specify custom primitive library pathTaoBi222022-11-171-2/+14
* Remove flattening from FABulous passTaoBi222022-11-171-11/+2
* Remove ALL currently unused flags (some to be reintroduced later and passed t...TaoBi222022-11-171-82/+3
* Add synth_fabulous ScriptPassTaoBi222022-11-178-0/+1282
* simlib: Simplify recently changed $mux modelJannis Harder2022-10-281-4/+2
* Merge pull request #3526 from jix/mux-simlib-evalJannis Harder2022-10-241-4/+1
|\
| * Consistent $mux undef handlingJannis Harder2022-10-241-4/+1
* | Add smtmap.v describing the smt2 backend's behavior for undef bitsJannis Harder2022-10-202-0/+29
|/
* Test fixes for latest iverilogMiodrag Milanovic2022-09-212-3/+2
* sf2: add NOTES about using yosys for smartfusion2 and igloo2Tristan Gingold2022-08-311-0/+84
* sf2: add a test for $alu gateTristan Gingold2022-08-311-0/+22
* sf2: suport $alu gate and ARI1 implementationTristan Gingold2022-08-312-2/+65
* synth_sf2: purge on last cleanTristan Gingold2022-08-311-2/+2
* sf2/cells_sim.v: add XTLOSC, SYSRESET cellsTristan Gingold2022-08-311-1/+110
* sf2/cells_sim.v: add IOSTD parameter to I/O cellsTristan Gingold2022-08-311-0/+11
* synth_sf2: add -discard-ffinit option to discard ff initial valueTristan Gingold2022-08-311-1/+11
* Fitting help messages to 80 character widthKrystalDelusion2022-08-246-20/+25
* Add the $anyinit cell and the formalff passJannis Harder2022-08-161-0/+17
* Order ports with default assignments firstSean Anderson2022-08-091-10/+38
* nexus: Fix BRAM mapping.Marcelina Kościelnicka2022-08-091-18/+56
* Merge pull request #3397 from pepijndevos/patch-2Miodrag Milanović2022-07-061-1/+0
|\
| * Apicula now supports lutramPepijn de Vos2022-07-031-1/+0
* | Fix static initialization, fixes mingw buildMiodrag Milanovic2022-07-041-20/+21
|/
* gatemate: Add LUT tree library scriptgatecat2022-06-276-6/+591
* gatemate: Add preliminary sim models for LUT tree structuresgatecat2022-06-271-0/+44
* Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.Marcelina Kościelnicka2022-06-024-7/+64
* gatemate: Fix minor issues with `memory_libmap` (#3343)Patrick Urban2022-05-272-28/+39
* gatemate: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-183-781/+927
* machxo2: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-187-1/+578
* efinix: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-183-90/+163
* anlogic: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-189-303/+585
* ice40: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-188-458/+293
* xilinx: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-1837-2269/+4525
* gowin: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-189-266/+576
* nexus: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-1810-517/+677
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 06:11:57 +0000