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* Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-2329-299/+1059
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| * Fix missing newline at end of fileClifford Wolf2019-08-221-1/+1
| * Merge pull request #1289 from mmicko/anlogic_fixesClifford Wolf2019-08-225-91/+162
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| | * Merge remote-tracking branch 'upstream/master' into anlogic_fixesMiodrag Milanovic2019-08-187-165/+37
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| | * | Proper arith for Anlogic and use standard passMiodrag Milanovic2019-08-125-91/+162
| * | | Fix missing newline at end of fileClifford Wolf2019-08-221-1/+1
| * | | Merge pull request #1281 from mmicko/efinixClifford Wolf2019-08-229-0/+798
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| | * | | Fix formatingMiodrag Milanovic2019-08-111-2/+2
| | * | | one bit enable signalMiodrag Milanovic2019-08-111-1/+1
| | * | | fix mixing signals on FF mappingMiodrag Milanovic2019-08-111-4/+4
| | * | | Replaced custom step with setundefMiodrag Milanovic2019-08-113-91/+1
| | * | | Fixed data widthMiodrag Milanovic2019-08-111-2/+2
| | * | | Adding new pass to fix carry chainMiodrag Milanovic2019-08-113-0/+124
| | * | | cleanupMiodrag Milanovic2019-08-111-4/+7
| | * | | Fix COMiodrag Milanovic2019-08-091-26/+24
| | * | | Merge remote-tracking branch 'upstream/master' into efinixMiodrag Milanovic2019-08-099-267/+303
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| | * | | | clock for ram trough gbufMiodrag Milanovic2019-08-041-0/+6
| | * | | | Added bram supportMiodrag Milanovic2019-08-046-1/+260
| | * | | | Custom step to add global clock buffersMiodrag Milanovic2019-08-034-1/+129
| | * | | | Initial EFINIX supportMiodrag Milanovic2019-08-035-0/+370
| * | | | | Missing newlineEddie Hung2019-08-201-1/+1
| * | | | | Merge pull request #1209 from YosysHQ/eddie/synth_xilinxEddie Hung2019-08-204-16/+19
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| | * \ \ \ \ Merge remote-tracking branch 'origin/master' into eddie/synth_xilinxEddie Hung2019-08-2026-343/+629
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| | * | | | | Update Makefile tooEddie Hung2019-07-181-2/+2
| | * | | | | Work in progress for renaming labels/options in synth_xilinxEddie Hung2019-07-183-14/+17
| * | | | | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactorEddie Hung2019-08-203-19/+41
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| | * | | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithroEddie Hung2019-08-193-6/+6
| | * | | | | Update abc_* attr in ecp5 and ice40Eddie Hung2019-08-162-11/+21
| | * | | | | Attach abc_scc_break, abc_carry_{in,out} attr to ports not modulesEddie Hung2019-08-161-8/+20
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| * | | | | Merge branch 'master' into eddie/pr1266_againwhitequark2019-08-181-15/+5
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| | * \ \ \ \ Merge pull request #1250 from bwidawsk/masterEddie Hung2019-08-161-15/+5
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| | | * | | | techlibs/intel: Clean up MakefileBen Widawsky2019-08-051-15/+5
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| * | | | | Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPEREddie Hung2019-08-121-1/+1
| * | | | | Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_ad...Eddie Hung2019-08-126-150/+32
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* | | | | move attributes to wiresMarcin Kościelnicki2019-08-136-283/+537
* | | | | minor review fixesMarcin Kościelnicki2019-08-131-1/+1
* | | | | review fixesMarcin Kościelnicki2019-08-131-18/+27
* | | | | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-136-71/+220
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* | | | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-106-32/+150
* | | | Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-105-20/+14
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| * | | | substr() -> compare()Eddie Hung2019-08-071-3/+3
| * | | | RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-1/+1
| * | | | Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-072-117/+252
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| * | | | | stoi -> atoiEddie Hung2019-08-073-3/+3
| * | | | | Fix spacingEddie Hung2019-08-061-3/+3
| * | | | | Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-061-1/+1
| * | | | | Make liberal use of IdString.in()Eddie Hung2019-08-061-14/+8
* | | | | | Merge pull request #1270 from YosysHQ/eddie/alu_lcu_docClifford Wolf2019-08-101-8/+36
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| * | | | | Reformat so it shows up/looks nice when "help $alu" and "help $alu+"Eddie Hung2019-08-091-25/+34
| * | | | | A bit more on where $lcu comes fromEddie Hung2019-08-091-0/+2
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