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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-04 12:17:55 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-04 12:17:55 +0200 |
| commit | 8a3329871ba7bab98982a101327b8375cd73344d (patch) | |
| tree | cceda6c3c2ab2cd780bd273fefdaaccf1df9ef36 /techlibs | |
| parent | cf96f41c6d9c405ddc039a8d0629731924b774ed (diff) | |
| download | yosys-8a3329871ba7bab98982a101327b8375cd73344d.tar.gz yosys-8a3329871ba7bab98982a101327b8375cd73344d.tar.bz2 yosys-8a3329871ba7bab98982a101327b8375cd73344d.zip | |
clock for ram trough gbuf
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/efinix/efinix_gbuf.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/techlibs/efinix/efinix_gbuf.cc b/techlibs/efinix/efinix_gbuf.cc index 50f84c30c..e75fb3f4d 100644 --- a/techlibs/efinix/efinix_gbuf.cc +++ b/techlibs/efinix/efinix_gbuf.cc @@ -38,6 +38,12 @@ static void handle_gbufs(Module *module) for (auto bit : sigmap(cell->getPort("\\CLK"))) clk_bits.insert(bit); } + if (cell->type == "\\EFX_RAM_5K") { + for (auto bit : sigmap(cell->getPort("\\RCLK"))) + clk_bits.insert(bit); + for (auto bit : sigmap(cell->getPort("\\WCLK"))) + clk_bits.insert(bit); + } } for (auto wire : vector<Wire*>(module->wires())) |