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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-11 13:59:39 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-11 13:59:39 +0200 |
| commit | ead2b52b5a123e2c93578555de394a7a406e1fa5 (patch) | |
| tree | 673a2295b6c7ce44aec898315f9554c4bd062f38 /techlibs | |
| parent | aa0c37722a99a308e64ea9581111adea2d97e46d (diff) | |
| download | yosys-ead2b52b5a123e2c93578555de394a7a406e1fa5.tar.gz yosys-ead2b52b5a123e2c93578555de394a7a406e1fa5.tar.bz2 yosys-ead2b52b5a123e2c93578555de394a7a406e1fa5.zip | |
one bit enable signal
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/efinix/brams_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/efinix/brams_map.v b/techlibs/efinix/brams_map.v index 3236f39a5..6786ae769 100644 --- a/techlibs/efinix/brams_map.v +++ b/techlibs/efinix/brams_map.v @@ -1,7 +1,7 @@ module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CFG_ABITS = 8; parameter CFG_DBITS = 20; - parameter CFG_ENABLE_A = 2; + parameter CFG_ENABLE_A = 1; parameter CLKPOL2 = 1; parameter CLKPOL3 = 1; |