| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | ecp5: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 9 | -466/+584 | |
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| * | Add missing parameters for ecp5 | Rick Luiken | 2022-04-25 | 2 | -1/+2 | |
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| * | gowin: Add oscillator primitives | Tim Pambor | 2022-03-28 | 1 | -0/+34 | |
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| * | xilinx: Add RAMB4* blackboxes | Marcelina Kościelnicka | 2022-03-21 | 2 | -1/+695 | |
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| * | gowin: add support for Double Data Rate primitives | YRabbit | 2022-03-14 | 1 | -0/+25 | |
| | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | |||||
| * | intel_alm: M10K write-enable is negative-true | Lofty | 2022-03-09 | 6 | -7/+28 | |
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| * | gowin: Remove unnecessary attributes | YRabbit | 2022-02-24 | 1 | -5/+0 | |
| | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | |||||
| * | gowin: Add support for true differential output | YRabbit | 2022-02-24 | 1 | -0/+11 | |
| | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | |||||
| * | ecp5: Do not use specify in generate in cells_sim.v. | Marcelina Kościelnicka | 2022-02-21 | 1 | -28/+15 | |
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| * | gowin: Add remaining block RAM blackboxes. | Marcelina Kościelnicka | 2022-02-12 | 1 | -72/+527 | |
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| * | gowin: Fix LUT RAM inference, add more models. | Marcelina Kościelnicka | 2022-02-09 | 2 | -41/+241 | |
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| * | ecp5: Fix DPR16X4 sim model. | Marcelina Kościelnicka | 2022-02-09 | 1 | -1/+1 | |
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| * | nexus: Fix arith_map CO signal. | Marcelina Kościelnicka | 2022-02-06 | 1 | -1/+1 | |
| | | | | | Fixes #3187. | |||||
| * | Fix the help message of synth_quicklogic. | Xing GUO | 2022-01-31 | 1 | -2/+2 | |
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| * | Add $bmux and $demux cells. | Marcelina Kościelnicka | 2022-01-28 | 2 | -24/+87 | |
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| * | nexus: Fix BB sim model | gatecat | 2022-01-19 | 1 | -2/+2 | |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| * | Removed dbits 8 since 9 will always be picked | Miodrag Milanovic | 2022-01-19 | 1 | -2/+0 | |
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| * | Merge pull request #3120 from Icenowy/anlogic-bram | Miodrag Milanović | 2022-01-19 | 6 | -1/+269 | |
| |\ | | | | | anlogic: support BRAM mapping | |||||
| | * | anlogic: support BRAM mapping | Icenowy Zheng | 2021-12-17 | 6 | -1/+269 | |
| | | | | | | | | | | | | | | | | | | | | | | | Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> | |||||
| * | | intel_alm: disable 256x40 M10K mode | Lofty | 2021-12-22 | 1 | -9/+3 | |
| |/ | | | | | This BRAM mode uses both address ports, making it effectively single-port. Since memory_bram can't presently map to single-port memories, remove it. | |||||
| * | intel_alm: preliminary Arria V support | Lofty | 2021-11-25 | 6 | -7/+199 | |
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| * | synth_gatemate Revert cascade A/B port mixup | Patrick Urban | 2021-11-13 | 2 | -12/+4 | |
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| * | synth_gatemate: Remove iob_map invokation | Patrick Urban | 2021-11-13 | 1 | -1/+0 | |
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| * | synth_gatemate: Add block RAM cascade support | Patrick Urban | 2021-11-13 | 2 | -112/+96 | |
| | | | | | | * add simulation model for block RAM cascade in 40K mode * limit 20K_SDP and 40K_SDP to 40 and 80 bits (the only useful configurations) | |||||
| * | synth_gatemate: Remove obsolete iob_map | Patrick Urban | 2021-11-13 | 3 | -61/+2 | |
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| * | synth_gatemate: Update pass | Patrick Urban | 2021-11-13 | 1 | -65/+25 | |
| | | | | | | | * remove `write_edif` and `write_blif` options * remove redundant `abc` call before muxcover * update style | |||||
| * | synth_gatemate: Remove specify blocks | Patrick Urban | 2021-11-13 | 1 | -92/+0 | |
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| * | synth_gatemate: Remove gatemate_bramopt pass | Patrick Urban | 2021-11-13 | 3 | -148/+0 | |
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| * | synth_gatemate: Revise block RAM read modes and initialization | Patrick Urban | 2021-11-13 | 3 | -71/+230 | |
| | | | | | | | | | * enable mixed read-width / write-width ports in SDP mode * fix NO_CHANGE and WRITE_THROUGH behavior during read access * remove redundant zero-initialization * set A/B_WE bit during map (gatemate_bramopt pass could be removed later) * differentiate "upper" and "lower" initialization for cascade mode | |||||
| * | synth_gatemate: Remove unsupported FF initialization | Patrick Urban | 2021-11-13 | 1 | -2/+0 | |
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| * | synth_gatemate: Rename multiplier factor parameters | Patrick Urban | 2021-11-13 | 1 | -13/+10 | |
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| * | synth_gatemate: Registers are uninitialized | Patrick Urban | 2021-11-13 | 2 | -3/+3 | |
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| * | synth_gatemate: Apply review remarks | Patrick Urban | 2021-11-13 | 5 | -279/+211 | |
| | | | | | | | | | * remove unused techmap models in `map_regs.v` * replace RAM initilization loops with 320-bit-writes * add script to test targets in top-level Makefile * remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v` * iterate over all modules in `gatemate_bramopt` pass | |||||
| * | synth_gatemate: Apply review remarks | Patrick Urban | 2021-11-13 | 5 | -141/+86 | |
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| * | synth_gatemate: Initial implementation | Patrick Urban | 2021-11-13 | 15 | -0/+3716 | |
| | | | | | Signed-off-by: Patrick Urban <patrick.urban@web.de> | |||||
| * | iopadmap: Add native support for negative-polarity output enable. | Marcelina Kościelnicka | 2021-11-09 | 9 | -33/+10 | |
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| * | synth_gowin: move splitnets to after iopadmap (#2435) | Pepijn de Vos | 2021-11-07 | 1 | -2/+3 | |
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| * | Remove noalu from synth_gowin json output as Apicula now supports it | Pepijn de Vos | 2021-11-07 | 1 | -1/+0 | |
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| * | gowin: widelut support (#3042) | Pepijn de Vos | 2021-11-06 | 1 | -1/+0 | |
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| * | ecp5: Add support for mapping aldff. | Marcelina Kościelnicka | 2021-10-27 | 2 | -13/+13 | |
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| * | Fixed Verific parser error in ice40 cell library | Claire Xenia Wolf | 2021-10-19 | 1 | -22/+62 | |
| | | | | | non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode | |||||
| * | CycloneV: Add (passthrough) support for cyclonev_oscillator | Olivier Galibert | 2021-10-17 | 1 | -1/+11 | |
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| * | CycloneV: Add (passthrough) support for ↵ | Olivier Galibert | 2021-10-17 | 1 | -0/+8 | |
| | | | | | cyclonev_hps_interface_mpu_general_purpose | |||||
| * | Hook up $aldff support in various passes. | Marcelina Kościelnicka | 2021-10-02 | 1 | -1/+1 | |
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| * | Add $aldff and $aldffe: flip-flops with async load. | Marcelina Kościelnicka | 2021-10-02 | 3 | -0/+382 | |
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| * | abc9: replace cell type/parameters if derived type already processed (#2991) | Eddie Hung | 2021-09-09 | 1 | -1/+1 | |
| | | | | | | | | | | | | * Add close bracket * Add testcase * Replace cell type/param if in unmap_design * Improve abc9_box error message too * Update comment as per review | |||||
| * | [ECP5] fix wrong link for syn_* attributes description (#2984) | kittennbfive | 2021-08-29 | 2 | -2/+2 | |
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| * | Add DLLDELD | ECP5-PCIe | 2021-08-22 | 1 | -0/+9 | |
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| * | Gowin: deal with active-low tristate (#2971) | Pepijn de Vos | 2021-08-20 | 4 | -6/+13 | |
| | | | | | | | | | | * deal with active-low tristate * remove empty port * update sim models * add expected lut1 to tests | |||||
| * | ice40: Fix typo in SB_CARRY specify for LP/UltraPlus | Sylvain Munaut | 2021-08-17 | 1 | -2/+2 | |
| | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
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index : iCE40/yosys | |
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