Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Merge pull request #3397 from pepijndevos/patch-2 | Miodrag Milanović | 2022-07-06 | 1 | -1/+0 |
|\ | | | | | Apicula now supports lutram | ||||
| * | Apicula now supports lutram | Pepijn de Vos | 2022-07-03 | 1 | -1/+0 |
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* | | Fix static initialization, fixes mingw build | Miodrag Milanovic | 2022-07-04 | 1 | -20/+21 |
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* | gatemate: Add LUT tree library script | gatecat | 2022-06-27 | 6 | -6/+591 |
| | | | | | Co-authored-by: Claire Xenia Wolf <claire@clairexen.net> Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | gatemate: Add preliminary sim models for LUT tree structures | gatecat | 2022-06-27 | 1 | -0/+44 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}. | Marcelina Kościelnicka | 2022-06-02 | 4 | -7/+64 |
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* | gatemate: Fix minor issues with `memory_libmap` (#3343) | Patrick Urban | 2022-05-27 | 2 | -28/+39 |
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* | gatemate: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 3 | -781/+927 |
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* | machxo2: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 7 | -1/+578 |
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* | efinix: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 3 | -90/+163 |
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* | anlogic: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 9 | -303/+585 |
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* | ice40: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 8 | -458/+293 |
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* | xilinx: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 37 | -2269/+4525 |
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* | gowin: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 9 | -266/+576 |
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* | nexus: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 10 | -517/+677 |
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* | ecp5: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 9 | -466/+584 |
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* | Add missing parameters for ecp5 | Rick Luiken | 2022-04-25 | 2 | -1/+2 |
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* | gowin: Add oscillator primitives | Tim Pambor | 2022-03-28 | 1 | -0/+34 |
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* | xilinx: Add RAMB4* blackboxes | Marcelina Kościelnicka | 2022-03-21 | 2 | -1/+695 |
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* | gowin: add support for Double Data Rate primitives | YRabbit | 2022-03-14 | 1 | -0/+25 |
| | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
* | intel_alm: M10K write-enable is negative-true | Lofty | 2022-03-09 | 6 | -7/+28 |
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* | gowin: Remove unnecessary attributes | YRabbit | 2022-02-24 | 1 | -5/+0 |
| | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
* | gowin: Add support for true differential output | YRabbit | 2022-02-24 | 1 | -0/+11 |
| | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
* | ecp5: Do not use specify in generate in cells_sim.v. | Marcelina Kościelnicka | 2022-02-21 | 1 | -28/+15 |
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* | gowin: Add remaining block RAM blackboxes. | Marcelina Kościelnicka | 2022-02-12 | 1 | -72/+527 |
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* | gowin: Fix LUT RAM inference, add more models. | Marcelina Kościelnicka | 2022-02-09 | 2 | -41/+241 |
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* | ecp5: Fix DPR16X4 sim model. | Marcelina Kościelnicka | 2022-02-09 | 1 | -1/+1 |
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* | nexus: Fix arith_map CO signal. | Marcelina Kościelnicka | 2022-02-06 | 1 | -1/+1 |
| | | | | Fixes #3187. | ||||
* | Fix the help message of synth_quicklogic. | Xing GUO | 2022-01-31 | 1 | -2/+2 |
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* | Add $bmux and $demux cells. | Marcelina Kościelnicka | 2022-01-28 | 2 | -24/+87 |
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* | nexus: Fix BB sim model | gatecat | 2022-01-19 | 1 | -2/+2 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Removed dbits 8 since 9 will always be picked | Miodrag Milanovic | 2022-01-19 | 1 | -2/+0 |
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* | Merge pull request #3120 from Icenowy/anlogic-bram | Miodrag Milanović | 2022-01-19 | 6 | -1/+269 |
|\ | | | | | anlogic: support BRAM mapping | ||||
| * | anlogic: support BRAM mapping | Icenowy Zheng | 2021-12-17 | 6 | -1/+269 |
| | | | | | | | | | | | | | | | | | | | | | | Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> | ||||
* | | intel_alm: disable 256x40 M10K mode | Lofty | 2021-12-22 | 1 | -9/+3 |
|/ | | | | | This BRAM mode uses both address ports, making it effectively single-port. Since memory_bram can't presently map to single-port memories, remove it. | ||||
* | intel_alm: preliminary Arria V support | Lofty | 2021-11-25 | 6 | -7/+199 |
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* | synth_gatemate Revert cascade A/B port mixup | Patrick Urban | 2021-11-13 | 2 | -12/+4 |
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* | synth_gatemate: Remove iob_map invokation | Patrick Urban | 2021-11-13 | 1 | -1/+0 |
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* | synth_gatemate: Add block RAM cascade support | Patrick Urban | 2021-11-13 | 2 | -112/+96 |
| | | | | | * add simulation model for block RAM cascade in 40K mode * limit 20K_SDP and 40K_SDP to 40 and 80 bits (the only useful configurations) | ||||
* | synth_gatemate: Remove obsolete iob_map | Patrick Urban | 2021-11-13 | 3 | -61/+2 |
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* | synth_gatemate: Update pass | Patrick Urban | 2021-11-13 | 1 | -65/+25 |
| | | | | | | * remove `write_edif` and `write_blif` options * remove redundant `abc` call before muxcover * update style | ||||
* | synth_gatemate: Remove specify blocks | Patrick Urban | 2021-11-13 | 1 | -92/+0 |
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* | synth_gatemate: Remove gatemate_bramopt pass | Patrick Urban | 2021-11-13 | 3 | -148/+0 |
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* | synth_gatemate: Revise block RAM read modes and initialization | Patrick Urban | 2021-11-13 | 3 | -71/+230 |
| | | | | | | | | * enable mixed read-width / write-width ports in SDP mode * fix NO_CHANGE and WRITE_THROUGH behavior during read access * remove redundant zero-initialization * set A/B_WE bit during map (gatemate_bramopt pass could be removed later) * differentiate "upper" and "lower" initialization for cascade mode | ||||
* | synth_gatemate: Remove unsupported FF initialization | Patrick Urban | 2021-11-13 | 1 | -2/+0 |
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* | synth_gatemate: Rename multiplier factor parameters | Patrick Urban | 2021-11-13 | 1 | -13/+10 |
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* | synth_gatemate: Registers are uninitialized | Patrick Urban | 2021-11-13 | 2 | -3/+3 |
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* | synth_gatemate: Apply review remarks | Patrick Urban | 2021-11-13 | 5 | -279/+211 |
| | | | | | | | | * remove unused techmap models in `map_regs.v` * replace RAM initilization loops with 320-bit-writes * add script to test targets in top-level Makefile * remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v` * iterate over all modules in `gatemate_bramopt` pass | ||||
* | synth_gatemate: Apply review remarks | Patrick Urban | 2021-11-13 | 5 | -141/+86 |
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* | synth_gatemate: Initial implementation | Patrick Urban | 2021-11-13 | 15 | -0/+3716 |
| | | | | Signed-off-by: Patrick Urban <patrick.urban@web.de> |