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Author
Age
Files
Lines
*
Work in progress for renaming labels/options in synth_xilinx
Eddie Hung
2019-07-18
3
-14
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+17
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Merge pull request #1208 from ZirconiumX/intel_cleanups
David Shah
2019-07-18
1
-29
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+14
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synth_intel: Use stringf
Dan Ravensloft
2019-07-18
1
-7
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+2
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synth_intel: s/not family/no family/
Dan Ravensloft
2019-07-18
1
-2
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+2
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intel_synth: Fix help message
Ben Widawsky
2019-07-18
1
-1
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+1
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intel_synth: Small code cleanup to remove if ladder
Ben Widawsky
2019-07-18
1
-28
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+10
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intel_synth: Make family explicit and match
Ben Widawsky
2019-07-18
1
-2
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+6
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intel_synth: Minor code cleanups
Ben Widawsky
2019-07-18
1
-2
/
+6
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synth_intel: rename for consistency with #1184
Dan Ravensloft
2019-07-18
1
-4
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+4
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Merge pull request #1184 from whitequark/synth-better-labels
Clifford Wolf
2019-07-18
5
-17
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+21
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synth_ecp5: rename dram to lutram everywhere.
whitequark
2019-07-16
4
-13
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+13
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synth_{ice40,ecp5}: more sensible pass label naming.
whitequark
2019-07-16
2
-5
/
+9
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Merge pull request #1204 from smunaut/fix_1187
David Shah
2019-07-17
2
-4
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+4
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ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
Sylvain Munaut
2019-07-16
2
-4
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+4
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gen_lut to return correctly sized LUT mask
Eddie Hung
2019-07-16
1
-1
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+1
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Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
Eddie Hung
2019-07-16
8
-29
/
+120
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$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
Eddie Hung
2019-07-15
7
-8
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+8
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ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT
Eddie Hung
2019-07-13
1
-9
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+7
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Use Const::from_string() not its constructor...
Eddie Hung
2019-07-12
1
-1
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+1
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Off by one
Eddie Hung
2019-07-12
1
-1
/
+1
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Fix spacing
Eddie Hung
2019-07-12
1
-1
/
+1
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Remove double push
Eddie Hung
2019-07-12
1
-1
/
+0
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Map to and from this box if -abc9
Eddie Hung
2019-07-12
1
-2
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+3
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ice40_opt to handle this box and opt back to SB_LUT4
Eddie Hung
2019-07-12
1
-0
/
+48
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Add new box to cells_sim.v
Eddie Hung
2019-07-12
1
-2
/
+25
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_ABC macro will map and unmap to this new box
Eddie Hung
2019-07-12
2
-0
/
+34
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Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box
Eddie Hung
2019-07-12
3
-25
/
+13
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Merge pull request #1183 from whitequark/ice40-always-relut
Clifford Wolf
2019-07-12
1
-11
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+5
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synth_ice40: switch -relut to be always on.
whitequark
2019-07-11
1
-10
/
+4
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synth_ice40: fix help text typo. NFC.
whitequark
2019-07-11
1
-1
/
+1
*
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Merge pull request #1182 from koriakin/xc6s-bram
Eddie Hung
2019-07-11
9
-8
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+598
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synth_xilinx: Initial Spartan 6 block RAM inference support.
Marcin KoĆcielnicki
2019-07-11
9
-8
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+598
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xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Viv...
Marcin KoĆcielnicki
2019-07-11
2
-6
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+6
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Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime
Eddie Hung
2019-07-10
3
-6
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+15
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Error out if -abc9 and -retime specified
Eddie Hung
2019-07-10
3
-6
/
+15
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Merge pull request #1148 from YosysHQ/xc7mux
Eddie Hung
2019-07-10
6
-49
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+414
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Add some spacing
Eddie Hung
2019-07-10
1
-9
/
+9
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Add some ASCII art explaining mux decomposition
Eddie Hung
2019-07-10
1
-0
/
+21
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Call muxpack and pmux2shiftx before cmp2lut
Eddie Hung
2019-07-09
1
-9
/
+12
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Restore opt_clean back to original place
Eddie Hung
2019-07-09
1
-2
/
+1
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Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
Eddie Hung
2019-07-09
1
-0
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+2
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Extend using A[1] to preserve don't care
Eddie Hung
2019-07-09
1
-1
/
+9
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Extend during mux decomposition with 1'bx
Eddie Hung
2019-07-09
1
-24
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+3
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Fix typo and comments
Eddie Hung
2019-07-09
1
-4
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+4
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-07-09
2
-19
/
+28
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synth_xilinx to call commands of synth -coarse directly
Eddie Hung
2019-07-09
1
-3
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+20
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Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""
Eddie Hung
2019-07-09
1
-2
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+2
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Fix spacing
Eddie Hung
2019-07-09
1
-1
/
+1
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*
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Fix spacing
Eddie Hung
2019-07-09
1
-1
/
+1
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Decompose mux inputs in delay-orientated (rather than area) fashion
Eddie Hung
2019-07-08
1
-18
/
+30
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