index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
techlibs
Commit message (
Expand
)
Author
Age
Files
Lines
*
Add "synth_xilinx -arch"
Clifford Wolf
2019-05-07
1
-1
/
+13
*
Merge remote-tracking branch 'origin/master' into clifford/specify
Eddie Hung
2019-05-03
6
-178
/
+124
|
\
|
*
Rename cells_map.v to prevent clash with ff_map.v
Eddie Hung
2019-05-03
1
-6
/
+8
|
*
Merge pull request #969 from YosysHQ/clifford/pmgenstuff
Clifford Wolf
2019-05-03
2
-0
/
+4
|
|
\
|
|
*
Run "peepopt" in generic "synth" pass and "synth_ice40"
Clifford Wolf
2019-04-30
2
-0
/
+4
|
*
|
Back to passing all xc7srl tests!
Eddie Hung
2019-05-01
1
-5
/
+4
|
*
|
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine
Eddie Hung
2019-05-01
3
-170
/
+104
|
|
\
\
|
|
*
\
Merge pull request #966 from YosysHQ/clifford/fix956
Clifford Wolf
2019-04-30
1
-1
/
+1
|
|
|
\
\
|
|
|
*
|
Add handling of init attributes in "opt_expr -undriven"
Clifford Wolf
2019-04-30
1
-1
/
+1
|
|
|
|
/
|
|
*
|
Refactor synth_xilinx to auto-generate doc
Eddie Hung
2019-04-26
1
-153
/
+95
|
|
*
|
Cleanup ice40
Eddie Hung
2019-04-26
1
-4
/
+6
|
|
|
/
|
*
|
WIP
Eddie Hung
2019-04-28
1
-36
/
+22
|
*
|
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
Eddie Hung
2019-04-28
2
-9
/
+12
|
*
|
Revert synth_xilinx 'fine' label more to how it used to be...
Eddie Hung
2019-04-26
1
-21
/
+40
|
*
|
Where did this check come from!?!
Eddie Hung
2019-04-26
1
-1
/
+0
|
|
/
*
|
Improve $specrule interface
Clifford Wolf
2019-04-23
1
-2
/
+2
*
|
Improve $specrule interface
Clifford Wolf
2019-04-23
1
-3
/
+4
*
|
Add $specrule cells for $setup/$hold/$skew specify rules
Clifford Wolf
2019-04-23
1
-0
/
+28
*
|
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...
Clifford Wolf
2019-04-23
1
-70
/
+70
*
|
Add $specify2 and $specify3 cells to simlib
Clifford Wolf
2019-04-23
1
-0
/
+147
|
/
*
Update help message
Eddie Hung
2019-04-22
1
-1
/
+1
*
Move 'shregmap -tech xilinx' into map_cells
Eddie Hung
2019-04-22
1
-17
/
+20
*
Merge remote-tracking branch 'origin/master' into xc7srl
Eddie Hung
2019-04-22
12
-21
/
+480
|
\
|
*
Merge pull request #941 from Wren6991/sim_lib_io_clke
Clifford Wolf
2019-04-22
1
-10
/
+19
|
|
\
|
|
*
ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware exp...
Luke Wren
2019-04-21
1
-10
/
+19
|
*
|
Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master
Clifford Wolf
2019-04-22
10
-10
/
+458
|
|
\
\
|
|
*
|
GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow
Diego
2019-04-12
10
-11
/
+459
|
|
|
/
|
*
|
Re-added clean after techmap in synth_xilinx
Clifford Wolf
2019-04-22
1
-0
/
+2
|
*
|
Merge pull request #916 from YosysHQ/map_cells_before_map_luts
Clifford Wolf
2019-04-22
1
-10
/
+10
|
|
\
\
|
*
\
\
Merge pull request #911 from mmicko/gowin-nobram
Clifford Wolf
2019-04-22
1
-1
/
+1
|
|
\
\
\
|
|
*
|
|
Make nobram false by default for gowin
Miodrag Milanovic
2019-04-02
1
-1
/
+1
*
|
|
|
|
Tidy up, fix for -nosrl
Eddie Hung
2019-04-21
2
-12
/
+16
*
|
|
|
|
Merge branch 'map_cells_before_map_luts' into xc7srl
Eddie Hung
2019-04-21
1
-2
/
+2
|
\
\
\
\
\
|
|
|
_
|
/
/
|
|
/
|
|
|
|
*
|
|
|
Merge branch 'master' into map_cells_before_map_luts
Eddie Hung
2019-04-21
6
-59
/
+85
|
|
\
|
|
|
*
|
|
|
|
Add comments
Eddie Hung
2019-04-21
1
-0
/
+7
*
|
|
|
|
Use new pmux2shiftx from #944, remove my old attempt
Eddie Hung
2019-04-21
1
-3
/
+8
*
|
|
|
|
Merge remote-tracking branch 'origin' into xc7srl
Eddie Hung
2019-04-20
4
-44
/
+69
|
\
\
\
\
\
|
|
|
/
/
/
|
|
/
|
|
|
|
*
|
|
|
Revert "synth_* with -retime option now calls abc with -D 1 as well"
Eddie Hung
2019-04-18
11
-15
/
+15
|
*
|
|
|
Merge branch 'master' into eddie/fix_retime
Eddie Hung
2019-04-18
4
-44
/
+69
|
|
\
\
\
\
|
|
|
|
_
|
/
|
|
|
/
|
|
|
|
*
|
|
Merge pull request #928 from litghost/add_xc7_sim_models
Eddie Hung
2019-04-12
3
-41
/
+60
|
|
|
\
\
\
|
|
|
*
|
|
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
Keith Rothman
2019-04-12
3
-52
/
+14
|
|
|
*
|
|
Fix LUT6_2 definition.
Keith Rothman
2019-04-09
1
-3
/
+3
|
|
|
*
|
|
Add additional cells sim models for core 7-series primatives.
Keith Rothman
2019-04-09
1
-0
/
+57
|
|
|
|
|
/
|
|
|
|
/
|
|
|
*
/
|
Fixing issues in CycloneV cell sim
Diego
2019-04-11
1
-3
/
+9
|
|
|
/
/
|
*
|
|
synth_* with -retime option now calls abc with -D 1 as well
Eddie Hung
2019-04-10
11
-15
/
+15
*
|
|
|
Call shregmap twice -- once for variable, another for fixed
Eddie Hung
2019-04-05
2
-8
/
+14
*
|
|
|
Move dffinit til after abc
Eddie Hung
2019-04-05
3
-2
/
+2
*
|
|
|
Merge branch 'eddie/fix_retime' into xc7srl
Eddie Hung
2019-04-05
4
-11
/
+12
|
\
|
|
|
|
*
|
|
Move techamp t:$_DFF_?N? to before abc call
Eddie Hung
2019-04-05
1
-2
/
+2
|
*
|
|
Retry
Eddie Hung
2019-04-05
1
-1
/
+1
[next]