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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-23 22:18:04 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-23 22:18:04 +0200 |
| commit | 4575e4ad86494e99dd05200f7242dfa632053c78 (patch) | |
| tree | 7e9d7b41dc8d873a6e6b1d2b927802dbffccdb8f /techlibs | |
| parent | 71c38d9de527e1a8b55ba295df459fbcf2a0fe47 (diff) | |
| download | yosys-4575e4ad86494e99dd05200f7242dfa632053c78.tar.gz yosys-4575e4ad86494e99dd05200f7242dfa632053c78.tar.bz2 yosys-4575e4ad86494e99dd05200f7242dfa632053c78.zip | |
Improve $specrule interface
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index facecd9a4..965242cdc 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1419,6 +1419,10 @@ endmodule module \$specrule (EN_SRC, EN_DST, SRC, DST); +parameter SKEW = 0; +parameter HOLD = 0; +parameter T_LIMIT = 0; + parameter SRC_WIDTH = 1; parameter DST_WIDTH = 1; @@ -1428,9 +1432,6 @@ parameter SRC_POL = 0; parameter DST_PEN = 0; parameter DST_POL = 0; -parameter LIMIT_GT = 0; -parameter T_LIMIT = 0; - input EN_SRC, EN_DST; input [SRC_WIDTH-1:0] SRC; input [DST_WIDTH-1:0] DST; |