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author | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 14:16:34 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 14:16:34 -0700 |
commit | d99422411f568d6d8d7de7d11346718e70012df4 (patch) | |
tree | 16eb67a26a1a9c09e86c23924702459a8e4017bf /techlibs | |
parent | 98781acf842e6184ae8991b6e48fdcdf18f4eaa9 (diff) | |
download | yosys-d99422411f568d6d8d7de7d11346718e70012df4.tar.gz yosys-d99422411f568d6d8d7de7d11346718e70012df4.tar.bz2 yosys-d99422411f568d6d8d7de7d11346718e70012df4.zip |
Use new pmux2shiftx from #944, remove my old attempt
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 57bde998f..4f02a47ea 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -112,9 +112,11 @@ struct SynthXilinxPass : public Pass log(" memory_map\n"); log(" dffsr2dff\n"); log(" dff2dffe\n"); - log(" opt -full\n"); log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n"); + log(" pmux2shiftx (without '-nosrl' only)\n"); + log(" opt_expr -mux_undef (without '-nosrl' only)\n"); log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n"); + log(" opt -full\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); log(" opt -fast\n"); log("\n"); @@ -261,17 +263,20 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "fine")) { - Pass::call(design, "opt -fast -full"); + Pass::call(design, "opt -fast"); Pass::call(design, "memory_map"); Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); - Pass::call(design, "opt -full"); if (!nosrl) { Pass::call(design, "simplemap t:$dff t:$dffe"); + Pass::call(design, "pmux2shiftx"); + Pass::call(design, "opt_expr -mux_undef"); Pass::call(design, "shregmap -tech xilinx -minlen 3"); } + Pass::call(design, "opt -full"); + if (vpr) { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); } else { |