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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-01 18:23:21 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-01 18:23:21 -0700 |
| commit | d394b9301b2619b8cb64f9faea4c112bf2a07925 (patch) | |
| tree | ac327aed5d77bfb0efd107bd436c931e7ee9cbe6 /techlibs | |
| parent | 31ff0d8ef529a1ddfa37e4b68017e4e433399da7 (diff) | |
| download | yosys-d394b9301b2619b8cb64f9faea4c112bf2a07925.tar.gz yosys-d394b9301b2619b8cb64f9faea4c112bf2a07925.tar.bz2 yosys-d394b9301b2619b8cb64f9faea4c112bf2a07925.zip | |
Back to passing all xc7srl tests!
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index dbafec301..8aa7b508e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -205,17 +205,16 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("fine")) { - run("opt -fast"); - run("memory_map"); - run("dffsr2dff"); - run("dff2dffe"); - // shregmap -tech xilinx can cope with $shiftx and $mux // cells for identifiying variable-length shift registers, // so attempt to convert $pmux-es to the former if (!nosrl || help_mode) run("pmux2shiftx", "(skip if '-nosrl')"); + run("opt -fast -full"); + run("memory_map"); + run("dffsr2dff"); + run("dff2dffe"); run("opt -full"); if (!vpr || help_mode) |