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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 11:38:23 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 11:38:23 -0700 |
| commit | ec88129a5cf510afc39ea12efa6059bed3eadfc3 (patch) | |
| tree | e53661f19130150b587bbd243a9a0480dbf0403c /techlibs | |
| parent | 0e76718720895a4985a7fad24052a61550acdeda (diff) | |
| download | yosys-ec88129a5cf510afc39ea12efa6059bed3eadfc3.tar.gz yosys-ec88129a5cf510afc39ea12efa6059bed3eadfc3.tar.bz2 yosys-ec88129a5cf510afc39ea12efa6059bed3eadfc3.zip | |
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Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index d6e7c2623..53eee7962 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -108,7 +108,7 @@ struct SynthXilinxPass : public Pass log(" techmap -map +/xilinx/drams_map.v\n"); log("\n"); log(" fine:\n"); - log(" opt -fast -full\n"); + log(" opt -fast\n"); log(" memory_map\n"); log(" dffsr2dff\n"); log(" dff2dffe\n"); |