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Author
Age
Files
Lines
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Fix spelling in -vpr help for synth_ice40
Tim Ansell
2017-12-08
1
-1
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+1
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Merge pull request #462 from daveshah1/up5k
Clifford Wolf
2017-11-28
1
-0
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+263
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Add remaining UltraPlus cells to ice40 techlib
David Shah
2017-11-28
1
-0
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+263
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Merge pull request #455 from daveshah1/up5k
Clifford Wolf
2017-11-18
1
-0
/
+103
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Remove unnecessary keep attributes
David Shah
2017-11-18
1
-5
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+5
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Merge branch 'master' into up5k
David Shah
2017-11-17
2
-5
/
+29
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Add some UltraPlus cells to ice40 techlib
David Shah
2017-11-16
1
-0
/
+103
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Merge pull request #453 from dh73/master
Clifford Wolf
2017-11-18
10
-5
/
+312
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Initial Cyclone 10 support
dh73
2017-11-08
5
-1
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+308
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Organizing Speedster file names
dh73
2017-11-08
5
-4
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+4
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Add "synth_ice40 -vpr"
Clifford Wolf
2017-11-16
2
-5
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+29
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Clean whitespace and permissions in techlibs/intel
Larry Doolittle
2017-10-05
21
-190
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+190
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Rename "write_verilog -nobasenradix" to "write_verilog -decimal"
Clifford Wolf
2017-10-03
1
-4
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+1
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Tested and working altsyncarm without init files
dh73
2017-10-01
2
-57
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+59
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Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ...
dh73
2017-10-01
30
-727
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+2954
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Add first draft of eASIC back-end
Clifford Wolf
2017-09-29
2
-0
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+191
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Fix synth_ice40 doc regarding -top default
Clifford Wolf
2017-09-29
1
-1
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+1
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Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.
Andrew Zonenberg
2017-09-14
2
-2
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+4
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Initial support for extraction of counters with clock enable
Andrew Zonenberg
2017-09-14
1
-21
/
+65
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Merge pull request #406 from azonenberg/coolrunner-techmap
Clifford Wolf
2017-09-02
2
-18
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+125
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coolrunner2: Finish fixing special-use p-terms
Robert Ou
2017-09-01
1
-8
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+20
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coolrunner2: Generate a feed-through AND term when necessary
Robert Ou
2017-09-01
1
-13
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+31
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coolrunner2: Initial fixes for special p-terms
Robert Ou
2017-09-01
2
-1
/
+81
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coolrunner2: Fix mapping of flip-flops
Robert Ou
2017-09-01
1
-1
/
+0
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coolrunner2: Combine some for loops together
Robert Ou
2017-09-01
1
-16
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+14
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Fixed typo in error message
Andrew Zonenberg
2017-09-01
1
-1
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+1
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Added blackbox $__COUNT_ cell model
Andrew Zonenberg
2017-09-01
2
-0
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+18
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Refactoring: moved modules still in cells_sim to cells_sim_wip
Andrew Zonenberg
2017-09-01
3
-136
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+138
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Merge branch 'master' of https://github.com/cliffordwolf/yosys into counter-e...
Andrew Zonenberg
2017-08-30
1
-34
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+34
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Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're multi-e...
Andrew Zonenberg
2017-08-28
1
-34
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+34
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extract_counter: Minor changes requested to comply with upstream policy, fixe...
Andrew Zonenberg
2017-08-30
2
-4
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+4
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Finished refactoring counter extraction to be nice and generic. Implemented t...
Andrew Zonenberg
2017-08-28
2
-1
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+69
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Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to ...
Andrew Zonenberg
2017-08-28
3
-515
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+1
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Fixed bug causing GP_SPI model to not synthesize
Andrew Zonenberg
2017-08-27
1
-2
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+2
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Fixed more issues with GreenPAK counter sim models
Andrew Zonenberg
2017-08-15
1
-19
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+23
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Updated PGEN model to have level triggered reset (matches actual hardware beh...
Andrew Zonenberg
2017-08-15
1
-4
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+4
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Fixed bug in GP_COUNTx model
Andrew Zonenberg
2017-08-15
1
-7
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+12
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Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high
Andrew Zonenberg
2017-08-15
1
-47
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+47
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Merge pull request #381 from azonenberg/countfix
Clifford Wolf
2017-08-14
4
-504
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+900
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Fixed typo in GP_COUNT8 sim model
Andrew Zonenberg
2017-08-14
1
-1
/
+1
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Fixed typo in error message
Andrew Zonenberg
2017-08-14
1
-1
/
+1
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Changed LEVEL resets for GP_COUNTx to be properly synthesizeable
Andrew Zonenberg
2017-08-14
1
-48
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+60
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Changed LEVEL resets to be edge triggered anyway
Andrew Zonenberg
2017-08-14
1
-4
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+4
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Added level-triggered reset support to GP_COUNTx simulation models
Andrew Zonenberg
2017-08-14
1
-2
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+68
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Fixed undeclared "count" in GP_COUNT8_ADV
Andrew Zonenberg
2017-08-14
1
-0
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+2
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Fixed undeclared "count" in GP_COUNT14_ADV
Andrew Zonenberg
2017-08-14
1
-0
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+2
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Fixed typo in last commit
Andrew Zonenberg
2017-08-14
1
-3
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+3
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Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock di...
Andrew Zonenberg
2017-08-14
2
-37
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+293
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Fixed typo in COUNT8 model
Andrew Zonenberg
2017-08-14
1
-2
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+2
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Moved GP_POR out of digital cells b/c it has delays
Andrew Zonenberg
2017-08-14
2
-21
/
+21
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