Merge pull request #453 from dh73/master

Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells

10 files changed, 312 insertions, 5 deletions

diff --git a/techlibs/achronix/Makefile.inc b/techlibs/achronix/Makefile.inc
index 4dfa59856..affe0334a 100755
--- a/techlibs/achronix/Makefile.inc
+++ b/techlibs/achronix/Makefile.inc
@@ -1,6 +1,6 @@
 
 OBJS += techlibs/achronix/synth_speedster.o
 
-$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_comb_speedster.v))
-$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map_speedster.v))
+$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_sim.v))
+$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map.v))
 
diff --git a/techlibs/achronix/speedster22i/cells_arith_speedster.v b/techlibs/achronix/speedster22i/cells_arith.v
index 9ef073f7c..9ef073f7c 100755
--- a/techlibs/achronix/speedster22i/cells_arith_speedster.v
+++ b/techlibs/achronix/speedster22i/cells_arith.v
diff --git a/techlibs/achronix/speedster22i/cells_map_speedster.v b/techlibs/achronix/speedster22i/cells_map.v
index fb26eabf0..fb26eabf0 100755
--- a/techlibs/achronix/speedster22i/cells_map_speedster.v
+++ b/techlibs/achronix/speedster22i/cells_map.v
diff --git a/techlibs/achronix/speedster22i/cells_comb_speedster.v b/techlibs/achronix/speedster22i/cells_sim.v
index 24c57c41a..24c57c41a 100755
--- a/techlibs/achronix/speedster22i/cells_comb_speedster.v
+++ b/techlibs/achronix/speedster22i/cells_sim.v
diff --git a/techlibs/achronix/synth_speedster.cc b/techlibs/achronix/synth_speedster.cc
index 8158c56fd..3808af6f1 100755
--- a/techlibs/achronix/synth_speedster.cc
+++ b/techlibs/achronix/synth_speedster.cc
@@ -122,7 +122,7 @@ struct SynthIntelPass : public ScriptPass {
   {
     if (check_label("begin"))
       {
-        run("read_verilog -sv -lib +/achronix/speedster22i/cells_comb_speedster.v");
+        run("read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v");
         run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
       }
 
@@ -164,7 +164,7 @@ struct SynthIntelPass : public ScriptPass {
     if (check_label("map_cells"))
       {
         run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I");
-        run("techmap -map +/achronix/speedster22i/cells_map_speedster.v");
+        run("techmap -map +/achronix/speedster22i/cells_map.v");
         run("dffinit -ff dffeas Q INIT");
         run("clean -purge");
       }
diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc
index 429d23677..ec7cea379 100644
--- a/techlibs/intel/Makefile.inc
+++ b/techlibs/intel/Makefile.inc
@@ -8,11 +8,13 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map.
 $(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_sim.v))
 $(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_sim.v))
 $(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_sim.v))
+$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_sim.v))
 $(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_sim.v))
 $(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_sim.v))
 $(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_map.v))
 $(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_map.v))
 $(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_map.v))
+$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_map.v))
 $(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_map.v))
 $(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_map.v))
 #$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/arith_map.v))
diff --git a/techlibs/intel/cyclone10/cells_arith.v b/techlibs/intel/cyclone10/cells_arith.v
new file mode 100644
index 000000000..5ae8d6cea
--- /dev/null
+++ b/techlibs/intel/cyclone10/cells_arith.v
@@ -0,0 +1,65 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// NOTE: This is still WIP.
+(* techmap_celltype = "$alu" *)
+module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
+   parameter A_SIGNED = 0;
+   parameter B_SIGNED = 0;
+   parameter A_WIDTH  = 1;
+   parameter B_WIDTH  = 1;
+   parameter Y_WIDTH  = 1;
+
+	input [A_WIDTH-1:0] A;
+	input [B_WIDTH-1:0] B;
+	output [Y_WIDTH-1:0] X, Y;
+
+	input CI, BI;
+	//output [Y_WIDTH-1:0] CO;
+        output                 CO;
+
+	wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
+
+	wire [Y_WIDTH-1:0] A_buf, B_buf;
+	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+	wire [Y_WIDTH-1:0] AA = A_buf;
+	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+	//wire [Y_WIDTH:0] C = {CO, CI};
+        wire [Y_WIDTH+1:0] COx;
+        wire [Y_WIDTH+1:0] C = {COx, CI};
+
+	/* Start implementation */
+	(* keep *) cyclone10lp_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
+
+	genvar i;
+	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
+	  if(i==Y_WIDTH-1) begin
+	    (* keep *) cyclone10lp_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
+            assign CO = COx[Y_WIDTH];
+          end
+	  else
+	    cyclone10lp_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
+	  end: slice
+	endgenerate
+	/* End implementation */
+	assign X = AA ^ BB;
+
+endmodule
diff --git a/techlibs/intel/cyclone10/cells_map.v b/techlibs/intel/cyclone10/cells_map.v
new file mode 100644
index 000000000..8ac5a55ec
--- /dev/null
+++ b/techlibs/intel/cyclone10/cells_map.v
@@ -0,0 +1,99 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+// Normal mode DFF negedge clk, negedge reset
+module  \$_DFF_N_ (input D, C, output Q);
+   parameter WYSIWYG="TRUE";
+   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+endmodule
+// Normal mode DFF
+module  \$_DFF_P_ (input D, C, output Q);
+   parameter WYSIWYG="TRUE";
+   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+endmodule
+
+// Async Active Low Reset DFF
+module  \$_DFF_PN0_ (input D, C, R, output Q);
+   parameter WYSIWYG="TRUE";
+   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+endmodule
+// Async Active High Reset DFF
+module  \$_DFF_PP0_ (input D, C, R, output Q);
+   parameter WYSIWYG="TRUE";
+   wire R_i = ~ R;
+   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+endmodule
+
+module  \$__DFFE_PP0 (input D, C, E, R, output Q);
+   parameter WYSIWYG="TRUE";
+   wire E_i = ~ E;
+   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
+endmodule
+
+// Input buffer map
+module \$__inpad (input I, output O);
+   cyclone10lp_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
+endmodule
+
+// Output buffer map
+module \$__outpad (input I, output O);
+   cyclone10lp_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
+endmodule
+
+// LUT Map
+/* 0 -> datac
+ 1 -> cin */
+module \$lut (A, Y);
+   parameter WIDTH  = 0;
+   parameter LUT    = 0;
+   input [WIDTH-1:0] A;
+   output            Y;
+   generate
+      if (WIDTH == 1) begin
+	 assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
+      end else
+        if (WIDTH == 2) begin
+           cyclone10lp_lcell_comb #(.lut_mask({4{LUT}}),
+                                   .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
+                                                                                .dataa(A[0]),
+                                                                                .datab(A[1]),
+                                                                                .datac(1'b1),
+                                                                                .datad(1'b1));
+        end else
+          if(WIDTH == 3) begin
+	     cyclone10lp_lcell_comb #(.lut_mask({2{LUT}}),
+                                     .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
+                                                                                  .dataa(A[0]),
+                                                                                  .datab(A[1]),
+                                                                                  .datac(A[2]),
+                                                                                  .datad(1'b1));
+          end else
+            if(WIDTH == 4) begin
+	       cyclone10lp_lcell_comb #(.lut_mask(LUT),
+                                       .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
+                                                                                    .dataa(A[0]),
+                                                                                    .datab(A[1]),
+                                                                                    .datac(A[2]),
+                                                                                    .datad(A[3]));
+            end else
+	             wire _TECHMAP_FAIL_ = 1;
+   endgenerate
+
+endmodule
+
+
diff --git a/techlibs/intel/cyclone10/cells_sim.v b/techlibs/intel/cyclone10/cells_sim.v
new file mode 100644
index 000000000..f5a8aee2b
--- /dev/null
+++ b/techlibs/intel/cyclone10/cells_sim.v
@@ -0,0 +1,137 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+module VCC (output V);
+   assign V = 1'b1;
+endmodule // VCC
+
+module GND (output G);
+   assign G = 1'b0;
+endmodule // GND
+
+/* Altera Cyclone 10 LP devices Input Buffer Primitive */
+module cyclone10lp_io_ibuf
+  (output o, input i, input ibar);
+   assign ibar = ibar;
+   assign o    = i;
+endmodule // cyclone10lp_io_ibuf
+
+/* Altera Cyclone 10 LP devices Output Buffer Primitive */
+module cyclone10lp_io_obuf
+  (output o, input i, input oe);
+   assign o  = i;
+   assign oe = oe;
+endmodule // cyclone10lp_io_obuf
+
+/* Altera Cyclone IV (E) 4-input non-fracturable LUT Primitive */
+module cyclone10lp_lcell_comb
+  (output combout, cout,
+   input dataa, datab, datac, datad, cin);
+
+   /* Internal parameters which define the behaviour
+    of the LUT primitive.
+    lut_mask define the lut function, can be expressed in 16-digit bin or hex.
+    sum_lutc_input define the type of LUT (combinational | arithmetic).
+    dont_touch for retiming || carry options.
+    lpm_type for WYSIWYG */
+
+   parameter lut_mask   = 16'hFFFF;
+   parameter dont_touch = "off";
+   parameter lpm_type   = "cyclone10lp_lcell_comb";
+   parameter sum_lutc_input = "datac";
+
+   reg [1:0]                        lut_type;
+   reg                              cout_rt;
+   reg                              combout_rt;
+   wire                             dataa_w;
+   wire                             datab_w;
+   wire                             datac_w;
+   wire                             datad_w;
+   wire                             cin_w;
+
+   assign dataa_w = dataa;
+   assign datab_w = datab;
+   assign datac_w = datac;
+   assign datad_w = datad;
+
+   function lut_data;
+      input [15:0]                  mask;
+      input                         dataa, datab, datac, datad;
+      reg [7:0]                     s3;
+      reg [3:0]                     s2;
+      reg [1:0]                     s1;
+      begin
+         s3 = datad ? mask[15:8] : mask[7:0];
+         s2 = datac ?   s3[7:4]  :   s3[3:0];
+         s1 = datab ?   s2[3:2]  :   s2[1:0];
+         lut_data = dataa ? s1[1] : s1[0];
+      end
+
+   endfunction
+
+   initial begin
+      if (sum_lutc_input == "datac") lut_type = 0;
+      else
+        if (sum_lutc_input == "cin")   lut_type = 1;
+        else begin
+           $error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
+           $finish();
+        end
+   end
+
+   always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
+      if (lut_type == 0) begin // logic function
+         combout_rt = lut_data(lut_mask, dataa_w, datab_w,
+                               datac_w, datad_w);
+      end
+      else if (lut_type == 1) begin // arithmetic function
+         combout_rt = lut_data(lut_mask, dataa_w, datab_w,
+                               cin_w, datad_w);
+      end
+      cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
+   end
+
+   assign combout = combout_rt & 1'b1;
+   assign cout = cout_rt & 1'b1;
+
+endmodule // cyclone10lp_lcell_comb
+
+/* Altera D Flip-Flop Primitive */
+module dffeas
+  (output q,
+   input d, clk, clrn, prn, ena,
+   input asdata, aload, sclr, sload);
+
+   // Timing simulation is not covered
+   parameter power_up="dontcare";
+   parameter is_wysiwyg="false";
+
+   reg   q_tmp;
+   wire  reset;
+   reg [7:0] debug_net;
+
+   assign reset       = (prn && sclr && ~clrn && ena);
+   assign q           = q_tmp & 1'b1;
+
+   always @(posedge clk, posedge aload) begin
+      if(reset)        q_tmp <= 0;
+      else q_tmp <= d;
+   end
+   assign q = q_tmp;
+
+endmodule // dffeas
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 9e4b33601..9b3e92b14 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -127,7 +127,7 @@ struct SynthIntelPass : public ScriptPass {
 
     if (!design->full_selection())
       log_cmd_error("This command only operates on fully selected designs!\n");
-    if (family_opt != "max10" && family_opt !="a10gx" && family_opt != "cyclonev" && family_opt !="cycloneiv" && family_opt !="cycloneive")
+    if (family_opt != "max10" && family_opt !="a10gx" && family_opt != "cyclonev" && family_opt !="cycloneiv" && family_opt !="cycloneive" && family_opt != "cyclone10")
       log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
 
     log_header(design, "Executing SYNTH_INTEL pass.\n");
@@ -148,6 +148,8 @@ struct SynthIntelPass : public ScriptPass {
           run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v");
         else if(check_label("family") && family_opt=="cyclonev")
           run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v");
+        else if(check_label("family") && family_opt=="cyclone10")
+          run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v");
         else if(check_label("family") && family_opt=="cycloneiv")
           run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
         else
@@ -211,6 +213,8 @@ struct SynthIntelPass : public ScriptPass {
           run("techmap -map +/intel/a10gx/cells_map.v");
         else if(family_opt=="cyclonev")
           run("techmap -map +/intel/cyclonev/cells_map.v");
+        else if(family_opt=="cyclone10")
+          run("techmap -map +/intel/cyclone10/cells_map.v");
         else if(family_opt=="cycloneiv")
           run("techmap -map +/intel/cycloneiv/cells_map.v");
         else