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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-15 00:50:31 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-15 09:18:36 -0700 |
| commit | e6eaf487b6d46804641c67325082210e6f3d6d64 (patch) | |
| tree | 21ea934aa5caab9dd6524b4bae917de349090ba0 /techlibs | |
| parent | 3a404be62a7b7fcc435857e20aa6c528f373b81c (diff) | |
| download | yosys-e6eaf487b6d46804641c67325082210e6f3d6d64.tar.gz yosys-e6eaf487b6d46804641c67325082210e6f3d6d64.tar.bz2 yosys-e6eaf487b6d46804641c67325082210e6f3d6d64.zip | |
Fixed more issues with GreenPAK counter sim models
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim_digital.v | 42 |
1 files changed, 23 insertions, 19 deletions
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v index 6fba941a0..043cd18d4 100644 --- a/techlibs/greenpak4/cells_sim_digital.v +++ b/techlibs/greenpak4/cells_sim_digital.v @@ -58,23 +58,25 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT); "RISING": begin always @(posedge CLK, posedge RST) begin - count <= count - 1'd1; - if(count == 0) - count <= COUNT_TO; - if(RST) - count <= 0; + count <= 0; + else begin + count <= count - 1'd1; + if(count == 0) + count <= COUNT_TO; + end end end "FALLING": begin always @(posedge CLK, negedge RST) begin - count <= count - 1'd1; - if(count == 0) - count <= COUNT_TO; - if(!RST) - count <= 0; + count <= 0; + else begin + count <= count - 1'd1; + if(count == 0) + count <= COUNT_TO; + end end end @@ -88,7 +90,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT); "LEVEL": begin always @(posedge CLK, posedge RST) begin if(RST) - count <= 0; + count <= 0; else begin count <= count - 1'd1; @@ -422,23 +424,25 @@ module GP_COUNT8( "RISING": begin always @(posedge CLK, posedge RST) begin - count <= count - 1'd1; - if(count == 0) - count <= COUNT_TO; - if(RST) count <= 0; + else begin + count <= count - 1'd1; + if(count == 0) + count <= COUNT_TO; + end end end "FALLING": begin always @(posedge CLK, negedge RST) begin - count <= count - 1'd1; - if(count == 0) - count <= COUNT_TO; - if(!RST) count <= 0; + else begin + count <= count - 1'd1; + if(count == 0) + count <= COUNT_TO; + end end end |