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author | Clifford Wolf <clifford@clifford.at> | 2017-10-03 17:31:21 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2017-10-03 17:31:21 +0200 |
commit | 65f91e51205fdd436c569c4795517160960ac700 (patch) | |
tree | 866f50f10a644202612aecce5ca07e48dec35102 /techlibs | |
parent | 4718e65763854d9870bf9b88a7c1b1e78e10f05f (diff) | |
download | yosys-65f91e51205fdd436c569c4795517160960ac700.tar.gz yosys-65f91e51205fdd436c569c4795517160960ac700.tar.bz2 yosys-65f91e51205fdd436c569c4795517160960ac700.zip |
Rename "write_verilog -nobasenradix" to "write_verilog -decimal"
Diffstat (limited to 'techlibs')
-rwxr-xr-x | techlibs/intel/synth_intel.cc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 4c4c13016..5f8b9c92a 100755 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -63,9 +63,6 @@ struct SynthIntelPass : public ScriptPass { log(" -retime\n"); log(" run 'abc' with -dff option\n"); log("\n"); - log(" -nobasenradix\n"); - log(" dump the VQM netlist in clearbox format for certain defparam primitives\n"); - log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); @@ -232,7 +229,7 @@ struct SynthIntelPass : public ScriptPass { if (check_label("vqm")) { if (!vout_file.empty() || help_mode) - run(stringf("write_verilog -attr2comment -defparam -nohex -nobasenradix -renameprefix syn_ %s", + run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s", help_mode ? "<file-name>" : vout_file.c_str())); } } |