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* gowin: Add remaining block RAM blackboxes.Marcelina Kościelnicka2022-02-121-72/+527
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* gowin: Fix LUT RAM inference, add more models.Marcelina Kościelnicka2022-02-092-41/+241
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* ecp5: Fix DPR16X4 sim model.Marcelina Kościelnicka2022-02-091-1/+1
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* nexus: Fix arith_map CO signal.Marcelina Kościelnicka2022-02-061-1/+1
| | | | Fixes #3187.
* Fix the help message of synth_quicklogic.Xing GUO2022-01-311-2/+2
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* Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-282-24/+87
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* nexus: Fix BB sim modelgatecat2022-01-191-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Removed dbits 8 since 9 will always be pickedMiodrag Milanovic2022-01-191-2/+0
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* Merge pull request #3120 from Icenowy/anlogic-bramMiodrag Milanović2022-01-196-1/+269
|\ | | | | anlogic: support BRAM mapping
| * anlogic: support BRAM mappingIcenowy Zheng2021-12-176-1/+269
| | | | | | | | | | | | | | | | | | | | | | Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | intel_alm: disable 256x40 M10K modeLofty2021-12-221-9/+3
|/ | | | | This BRAM mode uses both address ports, making it effectively single-port. Since memory_bram can't presently map to single-port memories, remove it.
* intel_alm: preliminary Arria V supportLofty2021-11-256-7/+199
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* synth_gatemate Revert cascade A/B port mixupPatrick Urban2021-11-132-12/+4
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* synth_gatemate: Remove iob_map invokationPatrick Urban2021-11-131-1/+0
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* synth_gatemate: Add block RAM cascade supportPatrick Urban2021-11-132-112/+96
| | | | | * add simulation model for block RAM cascade in 40K mode * limit 20K_SDP and 40K_SDP to 40 and 80 bits (the only useful configurations)
* synth_gatemate: Remove obsolete iob_mapPatrick Urban2021-11-133-61/+2
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* synth_gatemate: Update passPatrick Urban2021-11-131-65/+25
| | | | | | * remove `write_edif` and `write_blif` options * remove redundant `abc` call before muxcover * update style
* synth_gatemate: Remove specify blocksPatrick Urban2021-11-131-92/+0
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* synth_gatemate: Remove gatemate_bramopt passPatrick Urban2021-11-133-148/+0
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* synth_gatemate: Revise block RAM read modes and initializationPatrick Urban2021-11-133-71/+230
| | | | | | | | * enable mixed read-width / write-width ports in SDP mode * fix NO_CHANGE and WRITE_THROUGH behavior during read access * remove redundant zero-initialization * set A/B_WE bit during map (gatemate_bramopt pass could be removed later) * differentiate "upper" and "lower" initialization for cascade mode
* synth_gatemate: Remove unsupported FF initializationPatrick Urban2021-11-131-2/+0
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* synth_gatemate: Rename multiplier factor parametersPatrick Urban2021-11-131-13/+10
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* synth_gatemate: Registers are uninitializedPatrick Urban2021-11-132-3/+3
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* synth_gatemate: Apply review remarksPatrick Urban2021-11-135-279/+211
| | | | | | | | * remove unused techmap models in `map_regs.v` * replace RAM initilization loops with 320-bit-writes * add script to test targets in top-level Makefile * remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v` * iterate over all modules in `gatemate_bramopt` pass
* synth_gatemate: Apply review remarksPatrick Urban2021-11-135-141/+86
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* synth_gatemate: Initial implementationPatrick Urban2021-11-1315-0/+3716
| | | | Signed-off-by: Patrick Urban <patrick.urban@web.de>
* iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-099-33/+10
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* synth_gowin: move splitnets to after iopadmap (#2435)Pepijn de Vos2021-11-071-2/+3
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* Remove noalu from synth_gowin json output as Apicula now supports itPepijn de Vos2021-11-071-1/+0
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* gowin: widelut support (#3042)Pepijn de Vos2021-11-061-1/+0
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* ecp5: Add support for mapping aldff.Marcelina Kościelnicka2021-10-272-13/+13
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* Fixed Verific parser error in ice40 cell libraryClaire Xenia Wolf2021-10-191-22/+62
| | | | non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode
* CycloneV: Add (passthrough) support for cyclonev_oscillatorOlivier Galibert2021-10-171-1/+11
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* CycloneV: Add (passthrough) support for ↵Olivier Galibert2021-10-171-0/+8
| | | | cyclonev_hps_interface_mpu_general_purpose
* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-021-1/+1
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* Add $aldff and $aldffe: flip-flops with async load.Marcelina Kościelnicka2021-10-023-0/+382
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* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-091-1/+1
| | | | | | | | | | | * Add close bracket * Add testcase * Replace cell type/param if in unmap_design * Improve abc9_box error message too * Update comment as per review
* [ECP5] fix wrong link for syn_* attributes description (#2984)kittennbfive2021-08-292-2/+2
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* Add DLLDELDECP5-PCIe2021-08-221-0/+9
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* Gowin: deal with active-low tristate (#2971)Pepijn de Vos2021-08-204-6/+13
| | | | | | | | | * deal with active-low tristate * remove empty port * update sim models * add expected lut1 to tests
* ice40: Fix typo in SB_CARRY specify for LP/UltraPlusSylvain Munaut2021-08-171-2/+2
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Add v2 memory cells.Marcelina Kościelnicka2021-08-111-0/+169
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* Fixes xc7 BRAM36sMaciej Dudek2021-07-301-4/+6
| | | | | | UG473 from Xilinx states that 15 bit should always be set if RAMB isn't in cascade mode. Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-1/+1
| | | | Fixes #2061.
* memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-281-0/+24
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* ice40: Fix LUT input indices in opt_lut -dlogic (again).Marcelina Kościelnicka2021-07-101-1/+1
| | | | Fixes #2061.
* ecp5: Add DCSC blackboxgatecat2021-07-061-0/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix icestorm linksClaire Xenia Wolf2021-06-092-516/+516
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-096-6/+6
| | | | | | | | | | git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
* Fix files with CRLF line endingsClaire Xenia Wolf2021-06-092-349/+349
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