Commit message (Collapse) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Merge branch 'master' into eddie/pr1266_again | whitequark | 2019-08-18 | 1 | -15/+5 |
|\ | |||||
| * | Merge pull request #1250 from bwidawsk/master | Eddie Hung | 2019-08-16 | 1 | -15/+5 |
| |\ | | | | | | | techlibs/intel: Clean up Makefile | ||||
| | * | techlibs/intel: Clean up Makefile | Ben Widawsky | 2019-08-05 | 1 | -15/+5 |
| | | | | | | | | | | | | | | | | | | | | | Use GNU make's foreach iterator and remove nonexistent files. Gmake is already a requirement of the build system. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | ||||
* | | | Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-08-12 | 1 | -1/+1 |
| | | | |||||
* | | | Revert "Merge pull request #1280 from ↵ | Eddie Hung | 2019-08-12 | 6 | -150/+32 |
|/ / | | | | | | | | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f. | ||||
* | | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" | David Shah | 2019-08-10 | 6 | -32/+150 |
| | | |||||
* | | Merge pull request #1258 from YosysHQ/eddie/cleanup | Clifford Wolf | 2019-08-10 | 5 | -20/+14 |
|\ \ | | | | | | | Cleanup a few barnacles across codebase | ||||
| * | | substr() -> compare() | Eddie Hung | 2019-08-07 | 1 | -3/+3 |
| | | | |||||
| * | | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-07 | 1 | -1/+1 |
| | | | |||||
| * | | Merge remote-tracking branch 'origin/master' into eddie/cleanup | Eddie Hung | 2019-08-07 | 2 | -117/+252 |
| |\ \ | |||||
| * | | | stoi -> atoi | Eddie Hung | 2019-08-07 | 3 | -3/+3 |
| | | | | |||||
| * | | | Fix spacing | Eddie Hung | 2019-08-06 | 1 | -3/+3 |
| | | | | |||||
| * | | | Use std::stoi instead of atoi(<str>.c_str()) | Eddie Hung | 2019-08-06 | 1 | -1/+1 |
| | | | | |||||
| * | | | Make liberal use of IdString.in() | Eddie Hung | 2019-08-06 | 1 | -14/+8 |
| | | | | |||||
* | | | | Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc | Clifford Wolf | 2019-08-10 | 1 | -8/+36 |
|\ \ \ \ | | | | | | | | | | | Add a few comments to document $alu and $lcu | ||||
| * | | | | Reformat so it shows up/looks nice when "help $alu" and "help $alu+" | Eddie Hung | 2019-08-09 | 1 | -25/+34 |
| | | | | | |||||
| * | | | | A bit more on where $lcu comes from | Eddie Hung | 2019-08-09 | 1 | -0/+2 |
| | | | | | |||||
| * | | | | Add more comments | Eddie Hung | 2019-08-09 | 1 | -4/+18 |
| | | | | | |||||
| * | | | | Add a few comments to document $alu and $lcu | Eddie Hung | 2019-08-08 | 1 | -9/+12 |
| | |/ / | |/| | | |||||
* | | | | Allow whitebox modules to be overwritten | Eddie Hung | 2019-08-07 | 1 | -2/+0 |
| | | | | |||||
* | | | | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER | Eddie Hung | 2019-08-07 | 3 | -10/+17 |
| | | | | |||||
* | | | | Add test | Eddie Hung | 2019-08-07 | 1 | -1/+10 |
| | | | | |||||
* | | | | Remove ice40_unlut | Eddie Hung | 2019-08-07 | 2 | -107/+0 |
| | | | | |||||
* | | | | Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER | Eddie Hung | 2019-08-07 | 3 | -39/+14 |
|/ / / | |||||
* | | | Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes | David Shah | 2019-08-07 | 1 | -101/+244 |
|\ \ \ | | | | | | | | | ecp5: Make cells_sim.v consistent with nextpnr | ||||
| * | | | ecp5: Make cells_sim.v consistent with nextpnr | David Shah | 2019-08-07 | 1 | -101/+244 |
| |/ / | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | | Merge pull request #1249 from mmicko/anlogic_fix | Clifford Wolf | 2019-08-07 | 1 | -16/+8 |
|\ \ \ | |/ / |/| | | anlogic : Fix alu mapping | ||||
| * | | anlogic : Fix alu mapping | Miodrag Milanovic | 2019-08-03 | 1 | -16/+8 |
| |/ | |||||
* / | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs | Clifford Wolf | 2019-08-06 | 1 | -0/+19 |
|/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Merge pull request #1239 from mmicko/mingw_fix | Clifford Wolf | 2019-08-02 | 3 | -6/+6 |
|\ | | | | | Fix formatting for msys2 mingw build | ||||
| * | Fix formatting for msys2 mingw build using GetSize | Miodrag Milanovic | 2019-08-01 | 3 | -6/+6 |
| | | |||||
* | | RST -> RSTBRST for RAMB8BWER | Eddie Hung | 2019-07-29 | 1 | -3/+3 |
|/ | |||||
* | Merge branch 'ZirconiumX-synth_intel_m9k' | Clifford Wolf | 2019-07-25 | 4 | -5/+11 |
|\ | |||||
| * | intel: Map M9K BRAM only on families that have it | Dan Ravensloft | 2019-07-23 | 4 | -5/+12 |
| | | | | | | | | | | | | | | | | This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM. | ||||
* | | Merge pull request #1218 from ZirconiumX/synth_intel_iopads | Clifford Wolf | 2019-07-25 | 1 | -8/+8 |
|\ \ | | | | | | | intel: Make -noiopads the default | ||||
| * | | intel: Make -noiopads the default | Dan Ravensloft | 2019-07-24 | 1 | -8/+8 |
| | | | |||||
* | | | Merge pull request #1224 from YosysHQ/xilinx_fix_ff | Eddie Hung | 2019-07-25 | 1 | -2/+2 |
|\ \ \ | |/ / |/| | | xilinx: Fix missing cell name underscore in cells_map.v | ||||
| * | | xilinx: Fix missing cell name underscore in cells_map.v | David Shah | 2019-07-25 | 1 | -2/+2 |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | | ice40: Fix test_dsp_model.sh | David Shah | 2019-07-19 | 1 | -1/+1 |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | | ice40/cells_sim.v: Fix sign of J and K partial products | David Shah | 2019-07-19 | 1 | -5/+7 |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | | ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode | David Shah | 2019-07-19 | 1 | -2/+2 |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | | Add tests for all combinations of A and B signedness for comb mul | Eddie Hung | 2019-07-19 | 2 | -1/+229 |
| | | | |||||
* | | | Don't copy ref if exists already | Eddie Hung | 2019-07-19 | 1 | -1/+3 |
| |/ |/| | |||||
* | | Merge pull request #1208 from ZirconiumX/intel_cleanups | David Shah | 2019-07-18 | 1 | -29/+14 |
|\ \ | | | | | | | Assorted synth_intel cleanups from @bwidawsk | ||||
| * | | synth_intel: Use stringf | Dan Ravensloft | 2019-07-18 | 1 | -7/+2 |
| | | | |||||
| * | | synth_intel: s/not family/no family/ | Dan Ravensloft | 2019-07-18 | 1 | -2/+2 |
| | | | |||||
| * | | intel_synth: Fix help message | Ben Widawsky | 2019-07-18 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cyclonev has been a "supported" family since the initial commit. The old commit message suggested to use a10gx which is incorrect. Aside from the obvious lack of functional change due to this just being a help message, users who were previously using "a10gx" for "cyclonev" will also have no functional change by using "cyclonev" instead. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | ||||
| * | | intel_synth: Small code cleanup to remove if ladder | Ben Widawsky | 2019-07-18 | 1 | -28/+10 |
| | | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | ||||
| * | | intel_synth: Make family explicit and match | Ben Widawsky | 2019-07-18 | 1 | -2/+6 |
| | | | | | | | | | | | | | | | | | | | | | | | | The help and code default to MAX10 for the family, however the couple of if ladders defaulted to cycloneive. Fix this inconsistency and the next patch will clean it up. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | ||||
| * | | intel_synth: Minor code cleanups | Ben Widawsky | 2019-07-18 | 1 | -2/+6 |
| | | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net> |