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Author
Age
Files
Lines
*
Merged addition of SED makefile variable from github.com/Siesh1oo/yosys
Clifford Wolf
2014-03-11
1
-1
/
+1
*
Fixes for improved techmap of shifts with large B inputs
Clifford Wolf
2014-03-06
1
-8
/
+8
*
Strictly zero-extend unsigned A-inputs of shift operations in techmap
Clifford Wolf
2014-03-06
1
-4
/
+4
*
Improved techmap of shift with wide B inputs
Clifford Wolf
2014-03-06
1
-13
/
+37
*
Added $slice and $concat cell types
Clifford Wolf
2014-02-07
2
-0
/
+42
*
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf
2014-02-03
1
-13
/
+47
*
More changes to techlibs/common/simlib.v for LEC
Clifford Wolf
2014-01-31
1
-6
/
+11
*
Added test comments to techlibs/cmos/cmos_cells.lib
Clifford Wolf
2014-01-29
1
-0
/
+2
*
Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)
Clifford Wolf
2014-01-29
1
-105
/
+305
*
Added $assert cell
Clifford Wolf
2014-01-19
1
-0
/
+15
*
Fixed $lut simlib model for a wider range of tools
Clifford Wolf
2014-01-18
1
-10
/
+12
*
More changes to simlib to make it friendlier to a wider range of tools
Clifford Wolf
2014-01-18
1
-10
/
+14
*
Fixed a type in $mem model in simlib.v
Clifford Wolf
2014-01-18
1
-1
/
+1
*
Removed cases of trailing comma in stdcells.v
Clifford Wolf
2014-01-18
1
-3
/
+3
*
Added $bu0 cell to simlib.v
Clifford Wolf
2014-01-18
1
-0
/
+22
*
Added techlibs/common/pmux2mux.v
Clifford Wolf
2014-01-17
2
-1
/
+26
*
Various small cleanups in stdcells.v techmap code
Clifford Wolf
2013-12-31
1
-68
/
+38
*
Added $bu0 cell (for easy correct $eq/$ne mapping)
Clifford Wolf
2013-12-28
1
-4
/
+10
*
Added support for non-const === and !== (for miter circuits)
Clifford Wolf
2013-12-27
2
-0
/
+86
*
Using simplemap mappers from techmap
Clifford Wolf
2013-11-24
1
-714
/
+40
*
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
Clifford Wolf
2013-11-24
4
-20
/
+23
*
Added "techmap -share_map" option
Clifford Wolf
2013-11-24
1
-4
/
+4
*
Fixed xilinx/example_sim_counter test bench
Clifford Wolf
2013-11-24
1
-1
/
+1
*
Added more generic _TECHMAP_ wire mechanism to techmap pass
Clifford Wolf
2013-11-23
1
-1
/
+1
*
Updated abc
Clifford Wolf
2013-11-21
2
-0
/
+11
*
Install simlib in datdir
Clifford Wolf
2013-11-19
1
-0
/
+6
*
Added commented-out osu025 maping commands to cmos techmap example
Clifford Wolf
2013-11-18
1
-0
/
+5
*
Cleanups and bugfixes in response to new internal cell checker
Clifford Wolf
2013-11-11
2
-47
/
+43
*
Fixed techmap of $reduce_xnor with multi-bit outputs
Clifford Wolf
2013-11-07
1
-1
/
+7
*
Fixed techmap of $gt and $ge with multi-bit outputs
Clifford Wolf
2013-11-06
1
-2
/
+14
*
Improved width extension with regard to undef propagation
Clifford Wolf
2013-11-06
1
-11
/
+11
*
Added DFFSR cell to techlibs/cmos/cmos_cells.lib
Clifford Wolf
2013-10-31
2
-0
/
+26
*
[EXAMPLES] Ported the mojo counter example to Zynq ZED board.
James Walmsley
2013-10-27
4
-0
/
+56
*
Cleanups in xilinx examples
Clifford Wolf
2013-10-27
3
-144
/
+28
*
Added synth_xilinx command
Clifford Wolf
2013-10-27
2
-0
/
+219
*
Moved simple xilinx counter sim example to subdir
Clifford Wolf
2013-10-27
3
-0
/
+0
*
Xilinx mojo_counter example is now working
Clifford Wolf
2013-10-27
3
-4
/
+9
*
Renamed techlibs/xilinx7 to techlibs/xilinx
Clifford Wolf
2013-10-26
8
-0
/
+0
*
Improved xilinx mojo_counter example
Clifford Wolf
2013-10-26
2
-2
/
+5
*
Added another xilinx example (not funcional yet)
Clifford Wolf
2013-10-26
4
-0
/
+101
*
Bugfix in dffsr techmap rules
Clifford Wolf
2013-10-18
1
-8
/
+8
*
Added techmap rules for $sr, $dffsr and $dlatch
Clifford Wolf
2013-10-18
1
-0
/
+181
*
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
Clifford Wolf
2013-10-18
1
-0
/
+166
*
Added $sr, $dffsr and $dlatch cell types
Clifford Wolf
2013-10-18
1
-20
/
+76
*
Added map, par and bitgen to xlinx7 example
Clifford Wolf
2013-10-16
1
-2
/
+39
*
Moved common techlib files to techlibs/common
Clifford Wolf
2013-09-15
6
-7
/
+7
*
Added spice testbench to techlibs/cmos
Clifford Wolf
2013-09-14
4
-3
/
+73
*
Added spice backend
Clifford Wolf
2013-09-14
4
-0
/
+78
*
Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)
Clifford Wolf
2013-08-27
1
-2
/
+10
*
Added simple xilinx7 technology mapping files
Clifford Wolf
2013-08-22
4
-0
/
+167
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