diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-01-18 18:54:50 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-01-18 18:54:50 +0100 |
| commit | 4a9e133fabe85847f4cdaafed0b8024691be5395 (patch) | |
| tree | 70fd5d5b37f54aec6a7f781281126333ddd6d970 /techlibs | |
| parent | bef17eeb109dd2dc4eaba6eb808a0172c0c53265 (diff) | |
| download | yosys-4a9e133fabe85847f4cdaafed0b8024691be5395.tar.gz yosys-4a9e133fabe85847f4cdaafed0b8024691be5395.tar.bz2 yosys-4a9e133fabe85847f4cdaafed0b8024691be5395.zip | |
Fixed a type in $mem model in simlib.v
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index f3d652f0e..321119e37 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1036,7 +1036,7 @@ generate end end end else - if (RD_CLK_POLARITY[i] == 1) begin:rd_posclk + if (WR_CLK_POLARITY[i] == 1) begin:rd_posclk always @(posedge WR_CLK[i]) if (WR_EN[i]) begin data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ]; |