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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-07 00:58:06 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-07 00:58:06 +0100 |
| commit | 404b46674b3bfec73ecac484bbf56354fd66f2c8 (patch) | |
| tree | 74335bf2f1b79c6357fb5b5a60e9071c87bfc032 /techlibs | |
| parent | b41740060b28039c7e01fede41e6affb91867e02 (diff) | |
| download | yosys-404b46674b3bfec73ecac484bbf56354fd66f2c8.tar.gz yosys-404b46674b3bfec73ecac484bbf56354fd66f2c8.tar.bz2 yosys-404b46674b3bfec73ecac484bbf56354fd66f2c8.zip | |
Fixed techmap of $reduce_xnor with multi-bit outputs
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/stdcells.v | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/techlibs/common/stdcells.v b/techlibs/common/stdcells.v index ca73f5bcd..e37ad20d5 100644 --- a/techlibs/common/stdcells.v +++ b/techlibs/common/stdcells.v @@ -351,9 +351,15 @@ endgenerate assign buffer[0] = A[0]; \$_INV_ gate_inv ( .A(buffer[A_WIDTH-1]), - .Y(Y) + .Y(Y[0]) ); +generate + if (Y_WIDTH > 1) begin:V + assign Y[Y_WIDTH-1:1] = 0; + end +endgenerate + endmodule // -------------------------------------------------------- |