Renamed stdcells_sim.v to simcells.v and fixed blackbox.v

4 files changed, 23 insertions, 20 deletions

diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index e81d34fbc..e2e1ba25a 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -1,13 +1,21 @@
 
 EXTRA_TARGETS += techlibs/common/blackbox.v
 
-techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.v techlibs/common/stdcells_sim.v
-	cat techlibs/common/simlib.v techlibs/common/stdcells_sim.v | sed -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new
+techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.v techlibs/common/simcells.v
+	cat techlibs/common/simlib.v techlibs/common/simcells.v | sed -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new
 	mv techlibs/common/blackbox.v.new techlibs/common/blackbox.v
 
-EXTRA_TARGETS += share/simlib.v
+EXTRA_TARGETS += share/simlib.v share/simcells.v share/blackbox.v
 
 share/simlib.v: techlibs/common/simlib.v
 	mkdir -p share
 	cp techlibs/common/simlib.v share/simlib.v
 
+share/simcells.v: techlibs/common/simcells.v
+	mkdir -p share
+	cp techlibs/common/simcells.v share/simcells.v
+
+share/blackbox.v: techlibs/common/blackbox.v
+	mkdir -p share
+	cp techlibs/common/blackbox.v share/blackbox.v
+
diff --git a/techlibs/common/blackbox.sed b/techlibs/common/blackbox.sed
index 4e9a3a7c6..21693ecdd 100644
--- a/techlibs/common/blackbox.sed
+++ b/techlibs/common/blackbox.sed
@@ -1,4 +1,4 @@
 #!/bin/sed -r
-/^(wire|assign|reg)/ d;
-/^(genvar|always|initial)/,/^end/ d;
+/^(wire|assign|reg|event)/ d;
+/^(genvar|generate|always|initial)/,/^end/ d;
 s/ reg / /;
diff --git a/techlibs/common/stdcells_sim.v b/techlibs/common/simcells.v
index 88284a092..10a809db6 100644
--- a/techlibs/common/stdcells_sim.v
+++ b/techlibs/common/simcells.v
@@ -51,13 +51,8 @@ endmodule
 
 module \$_MUX_ (A, B, S, Y);
 input A, B, S;
-output reg Y;
-always @* begin
-	if (S)
-		Y = B;
-	else
-		Y = A;
-end
+output Y;
+assign Y = S ? B : A;
 endmodule
 
 module  \$_SR_NN_ (S, R, Q);
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index beb2b8857..b4440ea8d 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -31,13 +31,11 @@
  *
  */
 
-`define INPUT_A \
-input [A_WIDTH-1:0] A; \
-generate if (A_SIGNED) begin:A_BUF wire signed [A_WIDTH-1:0] val = A; end else begin:A_BUF wire [A_WIDTH-1:0] val = A; end endgenerate
+`define INPUT_A input [A_WIDTH-1:0] A; \
+  generate if (A_SIGNED) begin:A_BUF wire signed [A_WIDTH-1:0] val = A; end else begin:A_BUF wire [A_WIDTH-1:0] val = A; end endgenerate
 
-`define INPUT_B \
-input [B_WIDTH-1:0] B; \
-generate if (B_SIGNED) begin:B_BUF wire signed [B_WIDTH-1:0] val = B; end else begin:B_BUF wire [B_WIDTH-1:0] val = B; end endgenerate
+`define INPUT_B input [B_WIDTH-1:0] B; \
+  generate if (B_SIGNED) begin:B_BUF wire signed [B_WIDTH-1:0] val = B; end else begin:B_BUF wire [B_WIDTH-1:0] val = B; end endgenerate
 
 // --------------------------------------------------------
 
@@ -661,7 +659,7 @@ generate
 	end
 endgenerate
 
-always @*
+always @* begin
 	casez ({I[WIDTH-1], lut0_out, lut1_out})
 		3'b?11: O = 1'b1;
 		3'b?00: O = 1'b0;
@@ -669,6 +667,7 @@ always @*
 		3'b1??: O = lut1_out;
 		default: O = 1'bx;
 	endcase
+end
 
 endmodule
 
@@ -784,9 +783,10 @@ input EN;
 input [WIDTH-1:0] D;
 output reg [WIDTH-1:0] Q;
 
-always @*
+always @* begin
 	if (EN == EN_POLARITY)
 		Q <= D;
+end
 
 endmodule