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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-18 12:01:00 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-18 12:01:00 +0100 |
| commit | 97f2979bbae05cb8b4ead4522a8343a0b149c7a0 (patch) | |
| tree | 90b4ba30ec27b047789860b2aa930c9d8613d1e1 /techlibs | |
| parent | 7d52eb0ddb843afc67ec4bc23a3b25c6f74ef489 (diff) | |
| download | yosys-97f2979bbae05cb8b4ead4522a8343a0b149c7a0.tar.gz yosys-97f2979bbae05cb8b4ead4522a8343a0b149c7a0.tar.bz2 yosys-97f2979bbae05cb8b4ead4522a8343a0b149c7a0.zip | |
Added commented-out osu025 maping commands to cmos techmap example
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/cmos/counter.ys | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/techlibs/cmos/counter.ys b/techlibs/cmos/counter.ys index 81430f681..a784f3465 100644 --- a/techlibs/cmos/counter.ys +++ b/techlibs/cmos/counter.ys @@ -3,9 +3,14 @@ read_verilog counter.v read_verilog -lib cmos_cells.v proc;; memory;; techmap;; + dfflibmap -liberty cmos_cells.lib abc -liberty cmos_cells.lib;; +# http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib +# dfflibmap -liberty osu025_stdcells.lib +# abc -liberty osu025_stdcells.lib;; + write_verilog synth.v write_spice synth.sp |