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path:
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techlibs
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xilinx
/
cells_map.v
Commit message (
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)
Author
Age
Files
Lines
*
Restore $__XILINX_MUXF78 const optimisation
Eddie Hung
2019-06-28
1
-24
/
+24
*
Clean up trimming leading 1'bx in A during techmappnig
Eddie Hung
2019-06-28
1
-15
/
+9
*
Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-06-28
1
-4
/
+2
|
\
|
*
Reduce diff with upstream
Eddie Hung
2019-06-27
1
-4
/
+2
*
|
This optimisation doesn't seem to work...
Eddie Hung
2019-06-25
1
-24
/
+24
*
|
Reduce MuxFx resources in mux techmapping
Eddie Hung
2019-06-24
1
-10
/
+30
*
|
Reduce number of decomposed muxes during techmap
Eddie Hung
2019-06-24
1
-14
/
+11
*
|
Revert "Fix techmapping muxes some more"
Eddie Hung
2019-06-24
1
-4
/
+4
*
|
Fix techmapping muxes some more
Eddie Hung
2019-06-24
1
-4
/
+4
*
|
Fix mux techmapping
Eddie Hung
2019-06-24
1
-19
/
+20
*
|
Change synth_xilinx's -nomux to -minmuxf <int>
Eddie Hung
2019-06-24
1
-25
/
+41
*
|
Fix spacing
Eddie Hung
2019-06-21
1
-3
/
+3
*
|
Add $__XILINX_MUXF78 to preserve entire box
Eddie Hung
2019-06-21
1
-4
/
+12
*
|
Revert "Remove wide mux inference"
Eddie Hung
2019-06-14
1
-0
/
+120
|
/
*
Fix name clash
Eddie Hung
2019-06-13
1
-4
/
+8
*
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
Eddie Hung
2019-06-12
1
-0
/
+8
*
Remove wide mux inference
Eddie Hung
2019-06-12
1
-120
/
+0
*
$__XILINX_MUX_ -> $__XILINX_SHIFTX
Eddie Hung
2019-06-06
1
-9
/
+9
*
Fix muxcover and its techmapping
Eddie Hung
2019-06-06
1
-2
/
+2
*
Run muxpack and muxcover in synth_xilinx
Eddie Hung
2019-06-06
1
-0
/
+12
*
Cleanup
Eddie Hung
2019-06-05
1
-10
/
+0
*
Fix name clash
Eddie Hung
2019-06-04
1
-11
/
+11
*
Add mux_map.v for wide mux
Eddie Hung
2019-06-04
1
-21
/
+14
*
Fix/workaround symptom unveiled by #1023
Eddie Hung
2019-05-21
1
-4
/
+14
*
Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-05-21
1
-6
/
+8
|
\
|
*
Rename cells_map.v to prevent clash with ff_map.v
Eddie Hung
2019-05-03
1
-6
/
+8
*
|
Trim off leading 1'bx in A
Eddie Hung
2019-05-02
1
-7
/
+20
*
|
Add don't care optimisation
Eddie Hung
2019-05-02
1
-0
/
+11
*
|
Revert to pre-muxcover approach
Eddie Hung
2019-05-02
1
-17
/
+77
*
|
Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-05-02
1
-0
/
+8
|
\
|
|
*
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
Eddie Hung
2019-04-28
1
-0
/
+8
*
|
Fix spacing
Eddie Hung
2019-04-26
1
-4
/
+4
*
|
Try a different approach with 'muxcover'
Eddie Hung
2019-04-26
1
-67
/
+15
*
|
Cleanup superseded
Eddie Hung
2019-04-25
1
-11
/
+1
*
|
Tweak
Eddie Hung
2019-04-22
1
-1
/
+1
*
|
Fix for A_WIDTH == 2 but B_WIDTH==3
Eddie Hung
2019-04-22
1
-1
/
+1
*
|
Trim A_WIDTH by Y_WIDTH-1
Eddie Hung
2019-04-22
1
-1
/
+1
*
|
Add comment
Eddie Hung
2019-04-22
1
-0
/
+3
*
|
Fix for mux_case_* mappings
Eddie Hung
2019-04-22
1
-17
/
+9
*
|
Fix for non-pow2 width muxes
Eddie Hung
2019-04-22
1
-9
/
+18
*
|
Add synth_xilinx -nomux option
Eddie Hung
2019-04-22
1
-0
/
+2
*
|
Merge remote-tracking branch 'origin/xc7srl' into xc7mux
Eddie Hung
2019-04-22
1
-0
/
+125
|
\
|
|
*
Call shregmap twice -- once for variable, another for fixed
Eddie Hung
2019-04-05
1
-0
/
+3
|
*
techmap inside map_cells stage
Eddie Hung
2019-04-05
1
-1
/
+0
|
*
Use soft-logic, not LUT3 instantiation
Eddie Hung
2019-04-04
1
-4
/
+2
|
*
Cleanup comments
Eddie Hung
2019-04-04
1
-5
/
+4
|
*
Fine tune cells_map.v
Eddie Hung
2019-03-20
1
-19
/
+15
|
*
Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length
Eddie Hung
2019-03-19
1
-53
/
+20
|
*
Add support for variable length Xilinx SRL > 128
Eddie Hung
2019-03-19
1
-11
/
+67
|
*
Fix spacing
Eddie Hung
2019-03-19
1
-1
/
+1
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