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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 16:58:44 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 16:58:44 -0700 |
| commit | 69863f7698853d502f6d9bf810fcfda8fce87e6e (patch) | |
| tree | 09b5f176c96b6fac946eb5208f7111eeb23f6a51 /techlibs/xilinx/cells_map.v | |
| parent | 61161faefc731bfbb5b68b2458fbf7e087b16d78 (diff) | |
| download | yosys-69863f7698853d502f6d9bf810fcfda8fce87e6e.tar.gz yosys-69863f7698853d502f6d9bf810fcfda8fce87e6e.tar.bz2 yosys-69863f7698853d502f6d9bf810fcfda8fce87e6e.zip | |
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Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 1def7b973..38c8a49e7 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -170,6 +170,9 @@ module \$shiftx (A, B, Y); for (i = 0; i < Y_WIDTH; i++) \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A({{i{1'bx}}, A[A_WIDTH-1:i]}), .B(B), .Y(Y[i])); end + // If the LSB of B is constant zero (and Y_WIDTH is 1) then + // we can optimise by removing every other entry from A + // and popping the constant zero from B else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin wire [(A_WIDTH+1)/2-1:0] A_i; for (i = 0; i < (A_WIDTH+1)/2; i++) |