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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 16:12:32 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 16:12:32 -0700 |
| commit | 9156e18f9215f7e8e5a36e068b137b01810769b1 (patch) | |
| tree | e7703ddf841adbe49f765d3b60f9440f5ef76e11 /techlibs/xilinx/cells_map.v | |
| parent | 4cd8f0297381c5fb9fe3b8cbb22d4240f2aaae63 (diff) | |
| download | yosys-9156e18f9215f7e8e5a36e068b137b01810769b1.tar.gz yosys-9156e18f9215f7e8e5a36e068b137b01810769b1.tar.bz2 yosys-9156e18f9215f7e8e5a36e068b137b01810769b1.zip | |
Fix spacing
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 94a48dbc2..00a0b494b 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -76,7 +76,7 @@ module \$__SHREG_ (input C, input D, input [31:0] L, input E, output Q); if (&_TECHMAP_CONSTMSK_L_) assign Q = T4; else begin - MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(L[5])); + MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(L[5])); MUXF7 fpga_mux_1 (.O(T6), .I0(T4), .I1(1'b0 /* unused */), .S(L[5])); MUXF8 fpga_mux_2 (.O(Q), .I0(T5), .I1(T6), .S(L[6])); end |