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* $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserveEddie Hung2019-12-031-1/+1
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* ice40_opt to ignore (* keep *) -ed cellsEddie Hung2019-12-031-0/+5
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* Merge pull request #1490 from YosysHQ/clifford/autonameClifford Wolf2019-11-141-0/+1
|\ | | | | Add "autoname" pass and use it in "synth_ice40"
| * Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-131-0/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #1465 from YosysHQ/dave/ice40_timing_simClifford Wolf2019-11-141-14/+436
|\ \ | |/ |/| ice40: Support for post-place-and-route timing simulations
| * ice40: Add post-pnr ICESTORM_RAM model and fix FFsDavid Shah2019-10-231-2/+340
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ice40: Support for post-pnr timing simulationDavid Shah2019-10-231-12/+96
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #1452 from nakengelhardt/fix_dsp_mem_regClifford Wolf2019-10-221-0/+1
|\ \ | |/ |/| Call memory_dff before DSP mapping to reserve registers (fixes #1447)
| * Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-171-0/+1
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* | Makefile: don't assume python is called `python3`Sean Cross2019-10-191-1/+1
|/ | | | | | | | | | | | | | | | On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross <sean@xobs.io>
* Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0410-91/+90
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* Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-044-31/+3
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* OopsEddie Hung2019-10-041-1/+1
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* Ohmilord this wasn't added all this time!?!Eddie Hung2019-10-041-0/+29
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* Re-orderEddie Hung2019-09-271-1/+1
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* select onceEddie Hung2019-09-261-5/+7
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* Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-261-3/+5
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* Only wreduce on t:$addEddie Hung2019-09-251-1/+1
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* Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40Eddie Hung2019-09-201-2/+1
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* Revert "Move mul2dsp before wreduce"Eddie Hung2019-09-201-4/+5
| | | | This reverts commit e4f4f6a9d5cf8bb23870fc483f16f66c80ceebab.
* Move mul2dsp before wreduceEddie Hung2019-09-201-5/+4
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* Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2Eddie Hung2019-09-191-1/+3
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* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-052-22/+175
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| * Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-303-3/+3
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| * | Comment out SB_MAC16 arrival time for now, need to handle all its modesEddie Hung2019-08-281-1/+1
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| * | Add arrival for SB_MAC16.OEddie Hung2019-08-281-0/+1
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| * | Add arrival times for UEddie Hung2019-08-281-0/+26
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| * | LX -> LPEddie Hung2019-08-281-1/+1
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| * | Round not floorEddie Hung2019-08-281-21/+21
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| * | Add LP timingsEddie Hung2019-08-281-0/+26
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| * | LX -> LPEddie Hung2019-08-281-1/+1
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| * | Do not overwrite LUT paramEddie Hung2019-08-281-1/+0
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| * | Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrivalEddie Hung2019-08-282-1/+48
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| * | | Add arrival times for HX devicesEddie Hung2019-08-281-21/+114
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| * | | Specify ice40 family to cells_sim.v using defineEddie Hung2019-08-281-1/+8
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* | | | Merge branch 'master' into xc7dspDavid Shah2019-08-3011-175/+63
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| * | | Rename boxes tooEddie Hung2019-08-293-3/+3
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| * | | Do not overwrite LUT paramEddie Hung2019-08-281-1/+0
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| * | Trailing commaEddie Hung2019-08-281-1/+1
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| * | Adapt to $__ICE40_CARRY_WRAPPEREddie Hung2019-08-281-3/+5
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| * | Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with"Eddie Hung2019-08-281-0/+45
| |/ | | | | | | This reverts commit 2aedee1f0e0f6a6214241f51f5c12d4b67c3ef6f.
| * Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason withEddie Hung2019-08-281-45/+0
| | | | | | | | CARRY_WRAPPER in the same way since I0 and I3 could be used
| * Update box size and timingsEddie Hung2019-08-283-12/+12
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| * Update to new $__ICE40_CARRY_WRAPPEREddie Hung2019-08-281-11/+8
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| * Put abc_* attributes above portEddie Hung2019-08-231-2/+4
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| * Merge pull request #1304 from YosysHQ/eddie/abc9_refactorEddie Hung2019-08-201-2/+8
| |\ | | | | | | Refactor abc9 to use port attributes, not module attributes
| | * Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithroEddie Hung2019-08-191-2/+2
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| | * Update abc_* attr in ecp5 and ice40Eddie Hung2019-08-161-2/+8
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| * | Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPEREddie Hung2019-08-121-1/+1
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| * | Revert "Merge pull request #1280 from ↵Eddie Hung2019-08-126-150/+32
| |/ | | | | | | | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f.
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-21 01:41:28 +0000