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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 11:59:31 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-20 11:59:31 -0700 |
| commit | 14c03861b6d178c85d6963e673ed51bc142457e1 (patch) | |
| tree | 286a896ad2d60544fa40cddc69fdeccd72a805d9 /techlibs/ice40 | |
| parent | ba71e4f8f2279aed381bb024acb61ed793ca78c5 (diff) | |
| parent | 29e4c8bd06acf718328c76ec5d6c11e3274b21d1 (diff) | |
| download | yosys-14c03861b6d178c85d6963e673ed51bc142457e1.tar.gz yosys-14c03861b6d178c85d6963e673ed51bc142457e1.tar.bz2 yosys-14c03861b6d178c85d6963e673ed51bc142457e1.zip | |
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
Refactor abc9 to use port attributes, not module attributes
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 2205be27d..ab04808f4 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -141,8 +141,14 @@ module SB_CARRY (output CO, input I0, I1, CI); assign CO = (I0 && I1) || ((I0 || I1) && CI); endmodule -(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *) -module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI); +(* abc_box_id = 1, lib_whitebox *) +module \$__ICE40_FULL_ADDER ( + (* abc_carry *) output CO, + output O, + input A, + input B, + (* abc_carry *) input CI +); SB_CARRY carry ( .I0(A), .I1(B), |