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* $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserveEddie Hung2019-12-031-1/+1
* ice40_opt to ignore (* keep *) -ed cellsEddie Hung2019-12-031-0/+5
* Merge pull request #1490 from YosysHQ/clifford/autonameClifford Wolf2019-11-141-0/+1
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| * Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-131-0/+1
* | Merge pull request #1465 from YosysHQ/dave/ice40_timing_simClifford Wolf2019-11-141-14/+436
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| * ice40: Add post-pnr ICESTORM_RAM model and fix FFsDavid Shah2019-10-231-2/+340
| * ice40: Support for post-pnr timing simulationDavid Shah2019-10-231-12/+96
* | Merge pull request #1452 from nakengelhardt/fix_dsp_mem_regClifford Wolf2019-10-221-0/+1
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| * Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-171-0/+1
* | Makefile: don't assume python is called `python3`Sean Cross2019-10-191-1/+1
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* Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0410-91/+90
* Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-044-31/+3
* OopsEddie Hung2019-10-041-1/+1
* Ohmilord this wasn't added all this time!?!Eddie Hung2019-10-041-0/+29
* Re-orderEddie Hung2019-09-271-1/+1
* select onceEddie Hung2019-09-261-5/+7
* Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-261-3/+5
* Only wreduce on t:$addEddie Hung2019-09-251-1/+1
* Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40Eddie Hung2019-09-201-2/+1
* Revert "Move mul2dsp before wreduce"Eddie Hung2019-09-201-4/+5
* Move mul2dsp before wreduceEddie Hung2019-09-201-5/+4
* Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2Eddie Hung2019-09-191-1/+3
* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-052-22/+175
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| * Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-303-3/+3
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| * | Comment out SB_MAC16 arrival time for now, need to handle all its modesEddie Hung2019-08-281-1/+1
| * | Add arrival for SB_MAC16.OEddie Hung2019-08-281-0/+1
| * | Add arrival times for UEddie Hung2019-08-281-0/+26
| * | LX -> LPEddie Hung2019-08-281-1/+1
| * | Round not floorEddie Hung2019-08-281-21/+21
| * | Add LP timingsEddie Hung2019-08-281-0/+26
| * | LX -> LPEddie Hung2019-08-281-1/+1
| * | Do not overwrite LUT paramEddie Hung2019-08-281-1/+0
| * | Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrivalEddie Hung2019-08-282-1/+48
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| * | | Add arrival times for HX devicesEddie Hung2019-08-281-21/+114
| * | | Specify ice40 family to cells_sim.v using defineEddie Hung2019-08-281-1/+8
* | | | Merge branch 'master' into xc7dspDavid Shah2019-08-3011-175/+63
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| * | | Rename boxes tooEddie Hung2019-08-293-3/+3
| * | | Do not overwrite LUT paramEddie Hung2019-08-281-1/+0
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| * | Trailing commaEddie Hung2019-08-281-1/+1
| * | Adapt to $__ICE40_CARRY_WRAPPEREddie Hung2019-08-281-3/+5
| * | Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with"Eddie Hung2019-08-281-0/+45
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| * Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason withEddie Hung2019-08-281-45/+0
| * Update box size and timingsEddie Hung2019-08-283-12/+12
| * Update to new $__ICE40_CARRY_WRAPPEREddie Hung2019-08-281-11/+8
| * Put abc_* attributes above portEddie Hung2019-08-231-2/+4
| * Merge pull request #1304 from YosysHQ/eddie/abc9_refactorEddie Hung2019-08-201-2/+8
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| | * Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithroEddie Hung2019-08-191-2/+2
| | * Update abc_* attr in ecp5 and ice40Eddie Hung2019-08-161-2/+8
| * | Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPEREddie Hung2019-08-121-1/+1
| * | Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_ad...Eddie Hung2019-08-126-150/+32
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