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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 17:07:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 17:07:07 -0700 |
| commit | 129df7184a2b85553366f9d56e26ac4eaccc5a52 (patch) | |
| tree | 50db08c8a0a1c85677a80a9309f1139b37bc1f2b /techlibs/ice40 | |
| parent | fc727fa5c9e0a04a5dc1b4fcef652c5bca90b220 (diff) | |
| download | yosys-129df7184a2b85553366f9d56e26ac4eaccc5a52.tar.gz yosys-129df7184a2b85553366f9d56e26ac4eaccc5a52.tar.bz2 yosys-129df7184a2b85553366f9d56e26ac4eaccc5a52.zip | |
Update to new $__ICE40_CARRY_WRAPPER
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index c7f3bdad2..02726605f 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -142,15 +142,16 @@ module SB_CARRY (output CO, input I0, I1, CI); endmodule (* abc_box_id = 1, lib_whitebox *) -module \$__ICE40_FULL_ADDER ( +module \$__ICE40_CARRY_WRAPPER ( (* abc_carry *) output CO, output O, - input A, - input B, + input A, B, (* abc_carry *) - input CI + input CI, + input I0, I3, ); + parameter LUT = 0; SB_CARRY carry ( .I0(A), .I1(B), @@ -158,16 +159,12 @@ module \$__ICE40_FULL_ADDER ( .CO(CO) ); SB_LUT4 #( - // I0: 1010 1010 1010 1010 - // I1: 1100 1100 1100 1100 - // I2: 1111 0000 1111 0000 - // I3: 1111 1111 0000 0000 - .LUT_INIT(16'b 0110_1001_1001_0110) + .LUT_INIT(LUT) ) adder ( - .I0(1'b0), + .I0(I0), .I1(A), .I2(B), - .I3(CI), + .I3(I3), .O(O) ); endmodule |