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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 17:25:54 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 17:25:54 -0700 |
| commit | d46d38e4d5e1502ea5cb6075161c87bd837af9eb (patch) | |
| tree | 472545f25c766fe9f2ba7fa5eba060066a9d09bc /techlibs/ice40 | |
| parent | f5b4bc847c02d6c3e06c086a1375840ccac936cd (diff) | |
| download | yosys-d46d38e4d5e1502ea5cb6075161c87bd837af9eb.tar.gz yosys-d46d38e4d5e1502ea5cb6075161c87bd837af9eb.tar.bz2 yosys-d46d38e4d5e1502ea5cb6075161c87bd837af9eb.zip | |
Trailing comma
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 02726605f..2a7487f6b 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -149,7 +149,7 @@ module \$__ICE40_CARRY_WRAPPER ( input A, B, (* abc_carry *) input CI, - input I0, I3, + input I0, I3 ); parameter LUT = 0; SB_CARRY carry ( |